View HYB18H512321AF-12_161409.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Data Sheet, Rev. 1.73, Aug. 2005
www..com
HYB18H512321AF-12/14/16/20 HYB18H512321AFL14/16/20
512-Mbit GDDR3 Graphics RAM RoHS compliant
Memory Products
Never
stop
thinking.
www..com
Edition 2005-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2005. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Under no circumstances may the Infineon Technologies product as referred to in this data sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Infineon Technologies product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible).
HYB18H512321AF 512-Mbit GDDR3
www..com
HYB18H512321AF-12/14/16/20, HYB18H512321AFL14/16/20 Revision History: Previous Revision: Page 75 Rev. 1.73 Rev. 1.60 2005-08
Subjects (major changes since last revision) figure 61: changed DQ setting
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Data Sheet 3 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Table of Contents 1 1.1 1.2 2 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.5 2.5.1 2.5.2 2.6 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.3.1 4.6.3.2 4.6.4 4.6.5 4.6.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mirror Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Diagram and Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Diagram for One Activated Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Truth Table for more than one Activated Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Truth Table for CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disabling the scan feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Initilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan initilization for Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan initilization in regular SGRAM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Exit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable impedance output drivers and active terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . GDDR3 IO Driver and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Calibration for Driver and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Switching of DQ terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output impedance and Termination DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Set Command (EMRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination Rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vendor Code and Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank / Row Activation (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write - Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write - Consecutive Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gapless Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 11 12 13 15 16 16 17 20 20 21 22 23 23 23 27 27 28 30 31 31 33 33 34 36 36 37 38 38 38 38 38 39 40 41 41 41 42 42 42 43 45 45 47 48 48 49 50 51 52
Data Sheet
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
4.6.7 4.6.8 4.7 4.7.1 4.7.2 4.7.3 4.7.3.1 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.8 4.8.1 4.8.2 4.8.3 4.9 4.10 4.11 4.11.1 4.12 4.13 4.14 4.14.1 4.14.2 4.14.3 4.14.4 4.14.5 5 5.1 5.2 5.2.1 5.3 5.4 5.5 5.6 5.7 5.7.1 5.7.2 5.8 5.9 5.10 5.10.1 5.10.2 5.11 5.12 5.13 6 6.1 6.2
Write with Autoprecharge followed by Read / Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . Write followed by Precharge on same bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read - Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive Read Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gapless Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by Precharge on the same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Termination Disable (DTERDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS followed by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge (PRE/PREALL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Refresh Command (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Entry (SREFEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Exit (SREFEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency range in DLL off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization in DLL off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writes (WR) in DLL off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reads (RD) in DLL off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh in DLL off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings and Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Power & DC Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Clock DC and AC Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver IV characteristics at 40 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination IV Characteristic at 60 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination IV Characteristic at 120 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination IV Characteristic at 240 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Ratings ( HYB18H512321AF-12/14/16/20 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Ratings (HYB18H512321AFL14/16/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timings ( HYB18H512321AF-12/14/16/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timings ( HYB18H512321AFL14/16/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53 54 55 55 57 58 58 59 60 61 62 63 64 65 66 67 68 70 71 71 72 73 74 74 74 75 76 79 80 80 81 81 82 82 83 83 84 84 85 86 87 88 88 89 90 92 95
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Data Sheet
5
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 16 Figure 17 Figure 18 Figure 20 Figure 21 Figure 23 Figure 24 Figure 25 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 46 Figure 47 Figure 48 Figure 49 Figure 51 Figure 53 Figure 54 Figure 55 Figure 57 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Data Sheet Ballout 512Mbit GDDR3 Graphics RAM [Top View, MF = Low ] . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State diagram for one bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Block Diagram (Reference only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Capture Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Shift Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Initialization for Stand-Alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Initialization Sequence within regular SGRAM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Exit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Driver simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination update Keep Out time after Autorefresh command . . . . . . . . . . . . . . . . . . . . . . . . . . Self Calibration of PMOS and NMOS Legs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT Disable Timing during a READ command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing of Vendor Code and Revision ID Generation on DQ[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank Activating Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Four Window Active tFAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock, CKE and Command/Address Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Write Burst / DM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gapless Write Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive Write Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write followed by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Command followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Autoprecharge followed by Read or Read with Autoprecharge on another bank. . . . . . Write followed by Precharge on same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Read Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gapless Consecutive Read Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive Read Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Command followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by Precharge on the same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS Command followed by DTERDIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS Command followed by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS Command followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Refresh Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Entry Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL off: Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL off: Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write followed by Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL off: Read Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 15 20 23 26 26 28 29 30 32 33 34 35 36 37 38 39 40 41 43 44 44 46 47 48 49 50 51 52 53 54 56 57 58 59 60 61 62 63 64 65 66 67 69 70 71 71 72 73 74 75 76 77
Rev. 1.73, 2005-08
HYB18H512321AF 512-Mbit GDDR3
www..com
Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70
DLL off: Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Ohm Driver Pull-Down and Pull-Up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Ohm Active Termination Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-TFBGA 136 package (11mm x 14mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78 83 84 85 86 87 98
Data Sheet
7
Rev. 1.73, 2005-08
HYB18H512321AF 512-Mbit GDDR3
www..com
List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ball Assignment with Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent Autoprecharge 19 Function Truth Table I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Truth Table II (CKE Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Exit) Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Range of external resistance ZQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination Types and Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Number of Legs used for Terminator and Driver Self Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision ID and Vendor Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mapping of WDQS and DM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BA02, BA1 and BA0 precharge bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL off: General Timing Parameter for -16 and -20 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . General Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh Exit Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power & DC Operation Conditions.( 0 C Tc 85 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Logic Input Levels ( 0 C Tc 85 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Clock DC and AC Input conditions ( 0 C Tc 85 C) . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitances (VDDQ = 1.8V, TA = 25C, f= 1MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmed Driver IV Characterisitcs at 40 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmed Terminator Characteristics at 60 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmed Terminator Characteristics af 120 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmed Terminator Characteristic at 240 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Ratings ( 0 C Tc 85 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Ratings ( 0 C Tc 85 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters (HYB18H512321AF-12/14/16/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters (HYB18H512321AFL14/16/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-TFBGA 136 Package Thermal Resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 13 16 17
21 22 24 25 25 26 30 33 33 35 36 39 41 45 68 74 75 77 79 80 81 82 82 83 84 85 86 87 88 89 90 92 95 99
Data Sheet
8
Rev. 1.73, 2005-08
www..com
512-Mbit GDDR3 Graphics RAM
HYB18H512321AF HYB18H512321AF-12/14/16/20 HYB18H512321AFL14/16/20
1
1.1
* * * * * * * * * * * * * * * * * * * * * * * * *
Overview
Features
2.0 V VDDQ IO voltage HYB18H512321AF-12/14/16/20 2.0 V VDD core voltage HYB18H512321AF-12/14/16/20 1.8 V VDDQ IO voltage HYB18H512321AFL14/16/20 1.8 V VDD core voltage HYB18H512321AFL14/16/20 Organization: 2048K x 32 x 8 banks 4096 rows and 512 columns (128 burst start locations) per bank Differential clock inputs (CLK and CLK) CAS latencies of 7, 8, 9, 10, 11 Write latencies of 3, 4 Burst sequence with length of 4, 8. 4n prefetch Short RAS to CAS timing for Writes tRAS Lockout support tWR programmable for Writes with Auto-Precharge Data mask for write commands Single ended READ strobe (RDQS) per byte. RDQS edge-aligned with READ data Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data DLL aligns RDQS and DQ transitions with Clock Programmable IO interface including on chip termination (ODT) Autoprecharge option with concurrent autoprecharge support 8k Refresh (32ms) Autorefresh and Self Refresh PG-TFBGA 136 package (11mm x 14mm) Calibrated output drive. Active termination support RoHS Compliant Product1)
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Data Sheet
9
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Overview
Table 1
Ordering Information Organisation x32 Clock (MHz) 800/700/600/500 700/600/500 Package PG-TFBGA 136
Part Number1) HYB18H512321AF-12/14/16/20 HYB18H512321AFL14/16/20
1) HYB: designator for memory components 18H: VDDQ = 1.8 V 512: 512-Mbit density 32: Organization A: Product revision F: Lead- and Halogen-Free L: Low power product
1.2
Description
The Infineon 512-Mbit GDDR3 Graphics RAM is a high speed memory device, designed for high bandwidth intensive applications like PC graphics systems. The chip's 8 bank architecture is optimized for high speed. HYB18H512321AF uses a double data rate interface and a 4n-prefetch architecture. The GDDR3 interface transfers two 32 bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4n-prefetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clock-cycle data transfers at the I/O pins. Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are center-aligned with data for write commands. The HYB18H512321AF operates from a differential clock (CLK and CLK). Commands (addresses and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is referenced to both edges of RDQS. In this document references to 'the positive edge of CLK' imply the crossing of the positive edge of CLK and the negative edge of CLK. Similarly, the 'negative edge of CLK' refers to the crossing of the negative edge of CLK and the positive edge of CLK. References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar fashion. Read and write accesses to the HYB18H512321AF are burst oriented. The burst length is fixed to 4 and 8 and the two least significant bits of the burst address are 'Don't Care' and internally set to LOW. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the column location for the burst access. Each of the 8 banks consists of 4096 row locations and 512 column locations. An AUTO PRECHARGE function can be combined with READ and WRITE to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of the HYB18H512321AF allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. The "On Die Termination" interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register. The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (autocalibration) or to 35, 40 or 45 Ohms. Auto Refresh and Power Down with Self Refresh operations are supported. A standard JEDEC PG-TFBGA 136 package is used which enables ultra high speed data transfer rates and a simple upgrade path from former DDR Graphics SDRAM products. Data Sheet 10 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration
2
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
V DDQ V SSQ V DDQ V SSQ V DDQ V DD V SS V REF V SSA V DDA V SS V DD V DDQ V SSQ V DDQ V SSQ V DDQ
Figure 1
V DD
DQ0
V SS
DQ1
ZQ
A
MF
V SS
DQ9
V DD
DQ8
V DDQ V SSQ V DDQ V SSQ V DDQ V DD V SS V REF V SSA V DDA V SS V DD V DDQ V SSQ V DDQ V SSQ V DDQ
V SSQ V DDQ V SSQ V DDQ
CAS BA0
B
V SSQ V DDQ V SSQ V DDQ
CS BA1
DQ2
DQ3
C
DQ11
DQ10
WDQS0 RDQS0
D
RDQS1 WDQS1
DQ4
DM0
E
DM1
DQ12
DQ6
DQ5 DQ7
F G
DQ13 DQ15
DQ14
V SSQ
A1 RFU
V SSQ
A5 CK
RAS RFU
CKE
H J
WE
BA2 CK
V DDQ
A0
V DDQ
A4
A10
A2
K
A6
A8/AP
V SSQ
DQ24
DQ25
A11
L
A7
DQ17
V SSQ
DQ16
DQ27
A3
M
A9
DQ19
DQ26
DM3
V DDQ V SSQ V DDQ V SSQ
SEN
N
V DDQ V SSQ V DDQ V SSQ
RESET
DM2
DQ18
WDQS3 RDQS3
P
RDQS2 WDQS2
DQ28
DQ29
R
DQ21
DQ20
DQ30
DQ31
T
DQ23
DQ22
V DD
V SS
V
V SS
V DD
Ballout 512Mbit GDDR3 Graphics RAM [Top View, MF = Low ]
Data Sheet
11
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration
2.1
Table 2 Ball CLK, CLK
Ball Definition and Description
Ball Description Type Input Detailed Function Clock: CLK and CLK are differential clock inputs. Address and command inputs are latched on the positive edge of CLK. Graphics SDRAM outputs (RDQS, DQs) are referenced to CLK. CLK and CLK are not internally terminated. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock and input buffers. Taking CKE LOW provides Power Down. If all banks are precharged, this mode is called Precharge Power Down and Self Refresh mode is entered if a Auto Refresh command is issued. If at least one bank is open, Active Power Down mode is entered and no Self Refresh is allowed. All input receivers except CLK, CLK and CKE are disabled during Power Down. In Self Refresh mode the clock receivers are disabled too. Self Refresh Exit is performed by setting CKE asynchronously HIGH. Exit of Power Down without Self Refresh is accomplished by setting CKE HIGH with a positive edge of CLK. The value of CKE is latched asynchronously by Reset during Power On to determine the value of the termination resistor of the address and command inputs. CKE is not allowed to go LOW during a RD, a WR or a snoop burst. Chip Select: CS enables the command decoder when low and disables it when high. When the command decoder is disabled, new commands with the exeption of DTERDIS are ignored, but internal operations continue. CS is one of the four command balls. Command Inputs: Sampled at the positive edge of CLK, CAS, RAS, and WE define (together with CS) the command to be executed. Data Input/Output: The DQ signals form the 32 bit data bus. During READs the balls are outputs and during WRITEs they are inputs. Data is transferred at both edges of RDQS. Input Data Mask: The DM signals are input mask signals for WRITE data. Data is masked when DM is sampled HIGH with the WRITE data. DM is sampled on both edges of WDQS. DM0 is for DQ<0:7>, DM1 is for DQ<8:15>, DM2 is for DQ<16:23> and DM3 is for DQ<24:31>. Although DM balls are input-only, their loading is designed to match the DQ and WDQS balls.
CKE
Input
CS
Input
RAS, CAS, WE DQ<0:31> DM<0:3>
Input I/O Input
RDQS<0:3> Output Read Data Strobes: RDQSx are unidirectional strobe signals. During READs the RDQSx are transmitted by the Graphics SDRAM and edge-aligned with data. RDQS have preamble and postamble requirements. RDQS0 is for DQ<0:7>, RDQS1 for DQ<8:15>, RDQS2 for DQ<16:23> and RDQS3 for DQ<24:31>. WDQS<0:3> Input Write Data Strobes: WDQS are unidirectional strobe signals. During WRITEs the WDQS are generated by the controller and center aligned with data. WDQS have preamble and postamble requirements. WDQS0 is for DQ<0:7>, WDQS1 for DQ<8:15>, WDQS2 for DQ<16:23> and WDQS3 for DQ<24:31>. Bank Address Inputs: BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED MODE REGISTER SET commands. Address Inputs: During ACTIVATE, A0-A11 defines the row address. For READ/WRITE, A2-A7 and A9 defines the column address, and A8 defines the auto precharge bit. If A8 is HIGH, the accessed bank is precharged after execution of the column access. If A8 is LOW, AUTO PRECHARGE is disabled and the bank remains active. Sampled with PRECHARGE, A8 determines whether one bank is precharged (selected by BA<0:2>, A8 LOW) or all 8 banks are precharged (A8 HIGH). During (EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are sampled with the positive edge of CLK. 12 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
BA<0:2>
Input
A<0:11>
Input
Data Sheet
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration Table 2 Ball ZQ RES Ball Description Type Input Detailed Function ODT Impedance Reference: The ZQ ball is used to control the ODT impedance. Reset pin: The RES pin is a VDDQ CMOS input. RES is not internally terminated. When RES is at LOW state the chip goes into full reset. The chip stays in full reset until RES goes to HIGH state. The Low to High transition of the RES signal is used to latch the CKE value to set the value of the termination resistors of the address and command inputs. After exiting the full reset a complete initialization is required since the full reset set the internal settings to default. Mirror function pin: The MF pin is a VDDQ CMOS input. This pin must be hardwired on board either to a power or to a ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow for an easier routing on board for a back to back memory arrangement. Enables Boundary Scan Functionality. If Boundary Scan is not used PIN should be constantly connected to GND.
MF
Input
SEN VREF
Input
Supply Voltage Reference: VREF is the reference voltage input. Supply Power Supply: Power and Ground for the internal logic. VDD and VDDA must be provided by the same power rail. Shorted in the package. Supply I/O Power Supply: Isolated Power and Ground for the output buffers to provide improved noise immunity. Please do not connect No Connect and Reserved for Future Use balls.
VDD, VSS, VDDA, VSSA VDDQ, VSSQ
NC, RFU
2.2
Mirror Function
The GDDR3 Graphics RAM provides a ball mirroring feature that is enabled by applying a logic HIGH on ball MF. This function allows for efficient routing in a clam shell configuration. Depending of the logic state applied on MF, the command and address signals will be assigned to different balls. The default ball configuration (see Figure 1) correponds to MF = LOW. The DC level (HIGH or LOW) must be applied on the MF pin at power up and is not allowed to change after that. Table 3 shows the ball assignment as a function of the logic state applied on MF. Table 3 LOW H3 F4 H9 F9 H4 K4 H2 K3 M4 K9 H11 K10 Ball Assignment with Mirror Signal HIGH H10 F9 H4 F4 H9 K9 H11 K10 M9 K4 H2 K3 RAS CAS WE CS CKE A0 A1 A2 A3 A4 A5 A6
MF Logic State
Data Sheet
13
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration Table 3 LOW L9 K11 M9 K2 L4 G4 G9 H10 Ball Assignment with Mirror (cont'd) Signal HIGH L4 K2 M4 K11 L9 G9 G4 H3 A7 A8 A9 A10 A11 BA0 BA1 BA2
MF Logic State
Data Sheet
14
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration
2.3
Functional Block Diagram
A0-A7,A9, A8/AP, A10-A11 BA0-BA2
Address buffer
A8/AP
Row Addresses A0-A11, BA0-BA2
Column Addresses A2-A7,A9
CS C ontrol Logic & Timing G enerator Row Decoder Row Decoder Memory Bank 4 Memory 0 Bank Array Bank 0 4096 x 512 x 32 bit 4096 x 512 x 32 bit Row Decoder Row Decoder Memory Bank 5 Memory 1 Bank Array Bank 1 4096 x 512 x 32 bit 4096 x 512 x 32 bit Row Decoder Row Decoder Memory Bank 6 Memory 2 Bank Array Bank 2 4096 x 512 x 32 bit 4096 x 512 x 32 bit Sense Amplifiers and DD ata B us Buffer Sense Amplifiers and ata Bus Buffer Sense e Amplifiers and D ata Bus Buffer Sens Amplifiers and D ata Bus Buffer Sense Amplifiers and D ata Bus Buffer Sens e Amplifiers and D ata Bus B uffer Sense e Amplifiersand D ata Bus Buffer S ens Amplifiers and D ata Bus B uffer RAS CAS WE RES Row Decoder Row Decoder Memory Bank 7 Memory 3 Bank Array Bank 3 4096 x 512 x 32 bit 4096 x 512 x 32 bit
Mode R egis ter
Refresh Counter
Row Address Buffer
Column Address Buffer
C olumn D ecoder C olumn Decoder
Column Decoder C olumn Decoder
Column DDecoder C olumn ecoder
MF
ZQ
CKE CLK DLL CLK Output Buffers Input Buffers
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
D ata RD QS1 WD QS 1 D M1
D ata RD QS2 WD QS 2 D M2
Figure 2
Functional Block Diagram
Data Sheet
15
D ata RD QS3 WD QS 3 D M3
D ata RD QS 0 WDQ S0 D M0
C olumn D ecoder C olumn Decoder
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration
2.4 2.4.1
Commands Command Table
In the following table CKEn refers to the positive edge of CLK corresponding to the clock cycle when the command is given to the Graphics SDRAM. CKEn-1 refers to the previous positive edge of CLK. For all command and address inputs CKEn is implied. All input states or sequences not shown are illegal or reserved.
Table 4 Operation
Command Overview Code DESEL CKE CKE CS RAS CAS WE BA0 BA1 BA2 A8 n-1 n H H H L X H H H L L L H H H H L L L X H X L X X X H L H L L H L L L L H H L X H X L X X L H H H L L H H H L L L L H X H X H X X X X A2-7 A9-11 X Note
1)
Device Deselect
Data Terminator Disable No Operation Mode Register Set Extended Mode Register Set Bank Activate Read Write Precharge Precharge All Auto Refresh Power Down Mode Entry Self Refresh Entry Self Refresh Exit
DTERDIS H NOP MRS EMRS ACT RD WR PRE PREALL AREF H H H H H H H H H H H
H H H H H H H H H H H H L H L H
H L L L L L L L L L L L H L X L X
X X 0 1 BA BA BA BA BA BA X X X X X X
X X 0 0 BA BA BA BA BA BA X X X X X X
X X 0 0 BA BA BA BA BA BA X X X X X X
X X
X X
1)2)
OPCODE OPCODE Row Address L H L H L H X X X X X Col. Col. Col. Col. X X X X X X X
1)3)
1)4) 1)4) 1)4) 1)4) 1) 1) 1)5) 1)6)
Read w/ Autoprecharge RD/A Write w/ Autoprecharge WR/A
PWDNEN H
Power Down Mode Exit PWDNEX L SREFEN SREFEX H L
1)7) 1)8) 1)9)
1) X represents "Don't Care". 2) This command is invoked when a Read is issued on another DRAM rank placed on the same command bus. Cannot be in powerdown or self-refresh state. The Read command will cause the data termination to be disabled. Refer to Figure 14 for timing. 3) BA0 - BA2 provide bank address, A0 - A11 provide the row address. 4) BA0 - BA2 provide bank address, A2- A7, A9 provide the column address, A8/AP controls Auto Precharge. 5) Auto Refresh and Self Refresh Entry differ only by the state of CKE. 6) PWDNEN is selected by issuing a DESEL or NOP at the first positive CLK edge following the HIGH to LOW transition of CKE. 7) First possible valid command after tXPN. During tXPN only NOP or DESEL commands are allowed. 8) Self Refresh is selected by issuing AREF at the first positive CLK edge following the HIGH to LOW transition of CKE. 9) First possible valid command after tXSC. During tXSC only NOP or DESEL commands are allowed.
Abbreviations: BA: Bank Adress; Col.: Column Adress Data Sheet 16 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration
2.4.2
Table 5 Command DESEL NOP
Description of Commands
Description of Commands Description The DESEL function prevents new commands from being executed by the Graphics SDRAM. The Graphics SDRAM is effectively deselected. Operations in progress are not affected. The NOP command is used to perform a no operation to the Graphics SDRAM, which is selected (CS is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. The Mode Register is loaded via address inputs A0 - A11. For more details see "Mode Register Set Command (MRS)" on Page 40 . The MRS command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. The Extended Mode Register is loaded via address inputs A0 - A11. For more details see section "Extended Mode Register Set Command (EMRS)" on Page 37. The EMRS command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. The ACT command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 - BA2 inputs selects the bank, and the address provided in inputs A0 - A11 selects the row. This row remains active (or open) for accesses until a precharge (PRE, RD/A, or WR/A command) is issued to that bank. A precharge must be issued before opening a different row in the same bank. The RD command is used to initiate a burst read access to an active row. The value on the BA0 BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The row will remain open for subsequent accesses. For RD commands the value on A8 is set LOW. The RD/A command is used to initiate a burst read access to an active row. The value on the BA0 - BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end of the read burst. The same individual-bank precharge function is performed like it is described for the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. The user must not issue a new ACT command to the same bank until the precharge time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the earliest possible time as described in section "Reads (RD)" on Page 55. The WR command is used to initiate a burst write access to an active row. The value on the BA0 BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The row will remain open for subsequent accesses. For WR commands the value on A8 is set LOW. Input data appearing on the DQs is written to the memory array depending on the value on the DM input appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed for that byte / column location.
MRS
EMRS
ACT
RD
RD/A
WR
Data Sheet
17
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration Table 5 Command WR/A Description of Commands Description The WR/A command is used to initiate a burst write access to an active row. The value on the BA0, BA1 and BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end of the write burst. The same individual-bank precharge function is performed which is described for the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. The user is not allowed to issue a new ACT to the same bank until the precharge time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the earliest possible time as described in section "Writes (WR)" on Page 45. Input data appearing on the DQs is written to the memory array depending on the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. The PRE command is used to deactivate the open row in a particular bank. The bank will be available for a subsequent row access a specified time (tRP) after the PRE command is issued. Inputs BA0 - BA2 select the bank to be precharged. A8/AP is set to LOW. Once a bank has been precharged, it is in the idle state and must be activated again prior to any RD or WR commands being issued to that bank. A PRE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. The PREALL command is used to deactivate all open rows in the memory device. The banks will be available for a subsequent row access a specified time (tRP) after the PREALL command is issued. Once the banks have been precharged, they are in the idle state and must be activated prior to any read or write commands being issued. The PREALL command will be treated as a NOP for those banks where there is no open row, or if a previously open row is already in the process of precharging. PREALL is issued by a PRE command with A8/AP set to HIGH. The AREF is used during normal operation of the GDDR3 Graphics RAM to refresh the memory content. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AREF command. The HYB18H512321AF requires AREF cycles at an average periodic interval of tREFI(max). To improve efficiency a maximum number of eight AREF commands can be posted to one memory device (with tRFC from AREF to AREF) as described in section "Auto Refresh Command (AREF)" on Page 70. This means that the maximum absolute interval between any AREF command is 8 x tREFI(max). This maximum absolute interval is to allow the GDDR3 Graphics RAM output drivers and internal terminators to recalibrate, compensating for voltage and temperature changes. All banks must be in the idle state before issuing the AREF command. They will be simultaneously refreshed and return to the idle state after AREF is completed. tRFC is the minimum required time between an AREF command and a following ACT/AREF command. The Self Refresh function can be used to retain data in the GDDR3 Graphics RAM even if the rest of the system is powered down. When entering the Self Refresh mode by issuing the SREFEN command, the GDDR3 Graphics RAM retains data without external clocking. The SREFEN command is initiated like an AREF command except CKE is disabled (LOW). The DLL is automatically disabled upon entering Self Refresh mode and automatically enabled and reset upon exiting Self Refresh. (1000 cycles must then occur before a RD command can be issued) The active terminations remain enabled during Self Refresh. Input signals except CKE are "Don't Care". If two GDDR3 Graphics RAMs share the same Command and Address bus, Self Refresh may be entered only for the two devices at the same time.
PRE
PREALL
AREF
SREFEN
Data Sheet
18
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration Table 5 Command SREFEX Description of Commands Description The SREFEX command is used to exit the Self Refresh mode. The DLL is automatically enabled and resetted upon exiting. The procedure for exiting Self Refresh requires a sequence of commands. First CLK and CLK must be stable prior to CKE going from LOW to HIGH. Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXSNR is satisfied. This time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and output calibration is to apply NOPs for 1000 cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate. The PWDNEN command enables the power down mode. It is entered when CKE is set low together with a NOP/DESEL. The CKE signal is sampled at the rising edge of the clock. Once the power down mode is initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power consumption. The DLL remains active (unless disabled before with EMRS). All banks can be set to idle state or stay active. During Power Down Mode, refresh operations cannot be performed; therefore the refresh conditions of the chip have to be considered and if necessary Power Down state has to be left to perform an Auto Refresh cycle. If two GDDR3 Graphics RAMs share the same Command and Address bus, Power down may be entered only for the two devices at the same time. A CKE HIGH value sampled at a low to high transition of CLK is required to exit power down mode. Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXPN is satisfied. After tXPN any command can be issued, but it has to comply with the state in which the power down mode was entered. Data Termination Disable (Bus snooping for RD commands) : The Data Termination Disable Command is detected by the device by snooping the bus for RD commands excluding CS. The GDDR3 Graphics RAM will disable its Data terminators when a RD command is detected. The terminators are disabled starting at CL - 1 clocks after the RD command is detected and the duration is 4 clocks. In a two rank system, both DRAM devices will snoop the bus for RD commands to either device and both will disable their terminators if a RD command is detected. The command and address terminators are always enabled. See Figure 14 for an example of when the data terminators are disabled during a RD command. Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent Autoprecharge To Command RD or RD/A WR or WR/A PRE ACT RD/A RD or RD/A WR or WR/A PRE ACT Minimum delay to another bank (with concurrent autoprecharge) (WL + 2) x tCK + tWTR 2 x tCK Note
PWDNEN
PWDNEX
DTERDIS
Table 6
From Command WR/A
tCK tCK
2 x tCK (CL + 4 - WL) x tCK
tCK tCK
Data Sheet
19
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration
2.5 2.5.1
State Diagram and Truth Tables State Diagram for One Activated Bank
The following diagram shows all possible states and transitions for one activated bank. The other 7 banks of the Graphics SDRAM are assumed to be in idle state.
single bank
WR
ACTIVE
PRE WR/A RD/A PDEN PDEX
RD
ACT
MRS EMRS
IDLE
AUTO REFRESH SREX SREN
PDEN PDEX
active
POWER DOWN
precharge
SELF REFRESH
all banks
Figure 3 State diagram for one bank
Note: MRS, EMRS, AUTO REFRESH, SELF REFRESH and precharge POWER DOWN are only allowed if all 8 banks are idle.
Data Sheet
20
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration
2.5.2
Function Truth Table for more than one Activated Bank
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the chip's multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions are illegal. Notes 1-11 define the start and end of the actions belonging to a submitted command. This table is based on the assumption that there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank tRRD, tRTW and tWTR have to be taken always into account. Table 7 ACTIVE Function Truth Table I ongoing action on bank n ACTIVATE WRITE
3) 1)
Current State
possible action in parallel on bank m ACT, PRE, WRITE, WRITE/A, READ, READ/A 2) ACT, PRE, WRITE, WRITE/A, READ, READ/A4) ACT, PRE, WRITE, WRITE/A, READ 6) ACT, PRE, WRITE, WRITE/A, READ, READ/A8) ACT, PRE, WRITE, WRITE/A, READ, READ/A 8) ACT, PRE, WRITE, WRITE/A, READ, READ/A 11) -
WRITE/A 5) READ 7) READ/A 9) PRECHARGE 10) PRECHARGE ALL 10) POWER DOWN ENTRY IDLE ACTIVATE
1) 12)
ACT 14)
POWER DOWN ENTRY 12) AUTO REFRESH
13) 12)
SELF REFRESH ENTRY EXTENDED MRS POWER DOWN SELF REFRESH
14) 15) 16)
MODE REGISTER SET (MRS) POWER DOWN EXIT
-
SELF REFRESH EXIT
1) Action ACTIVATE starts with issuing the command and ends after tRCD. 2) During action ACTIVATE an ACT command on another bank is allowed considering tRRD, a PRE command on another bank is allowed any time. WR, WR/A, RD and RD/A are always allowed. 3) Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge. 4) during action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank must be separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before tWTR is met. 5) Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling WDQS edge. 6) during action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank has to be separated by at least one NOP from the ongoing command. RD is not allowed before tWTR is met. RD/A is not allowed during an ongoing WRITE/A action. 7) Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS. 8) during action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to meet tRTW. 9) Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS. 10) Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after tRP. 11) During Action ACTIVE an ACT command on another banks is allowed considering tRRD. A PRE command on another bank is allowed any time. WR, WR/A, RD and RD/A are always allowed. 12) During POWER DOWN and SELF REFRESH only the EXIT commands are allowed.
Data Sheet
21
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Pin Configuration
13) AUTO REFRESH starts with issuing the command and ends after tRFC. 14) Actions MODE REGISTER SET and EXTENDED MODE REGISTER SET start with issuing the command and ends after tMRD. 15) Action POWER DOWN EXIT starts with issuing the command and ends after tXPN. 16) Action SELF REFRESH EXIT starts with issuing the command and ends after tXSC.
2.6
Table 8 CKE n-1 L L H
Function Truth Table for CKE
Function Truth Table II (CKE Table) CKE n L H L CURRENT STATE Power Down Self Refresh Power Down Self Refresh All Banks Idle Bank(s) Active All Banks Idle COMMAND X X DESEL or NOP DESEL or NOP DESEL or NOP DESEL or NOP Auto Refresh ACTION stay in Power Down stay in Self Refresh Exit Power Down Exit Self Refresh 5 Entry Precharge Power Down Entry Active Power Down Entry Self Refresh
Note: 1. 2. 3. 4. 5. CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the GDDR3 Graphics RAM immediatly prior to clock edge n. COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND. All states and sequences not shown are illegal or reserved. DESEL or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum of 1000 clock cycles is required before applying any other valid command.
Data Sheet
22
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Boundary Scan
3
3.1
Boundary Scan
General Description
The 512Mb GDDR3 incorporates a modified boundary scan test mode. This mode doesn't operate in accordance with IEEE Standard 1149.1-1990. To save the current GDDR3 ball-out, this mode will scan the parallel data input and output the scanned data through the WDQS0 pin controlled by SEN.
3.2
Disabling the scan feature
It is possible to operate the 512Mb GDDR3 without using the boundary scan feature. SEN (at U-4 of 136- ball package) should be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF, WDQS0 and CS will be operating at normal GDDR3 functionalities when SEN is deasserted.
Dedicated Scan Flops (1 per signal under test) Tie to logic 0 DM0 D DQ CK
Pins under test DQ5 D DQ CK
DQ4
D DQ CK
The following lists the rest of the signals on the scan chain: DQ[3:0], DQ[31:6], RDQS[3:1], WDQS[3:1], DM[3:1], CAS, WE, CKE, BA[2:0], A[11:0], CK, CK and ZQ D DQ CK Two RFU's (J-2 and J-3 on 136-ball package) will be on the scan chain and will read as a logic "0" The following lists the signals not on the scan chain: VDD, VSS, VDDQ, VSSQ, VDDA, VSSA and VREF
RDQS0 RES (SSH, Scan Shift) CS (SCK, Scan Clock) WDQS0 (SOUT, Scan Out) SEN, Scan Enable MF (SOE, Output Enable)
Puts device into scan mode and re-maps pins to scan functionality
Figure 4 Data Sheet
Internal Block Diagram (Reference only) 23 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Boundary Scan
Table 9 BIT# 1 2 3 4 5 6 7 8 9 10 11 12 Notes
Boundary Scan Exit) Order BALL D-3 C-2 C-3 B-2 B-3 A-4 B-10 B-11 C-10 C-11 D-10 D-11 BIT# 13 14 15 16 17 18 19 20 21 22 23 24 BALL E-10 F-10 E-11 G-10 F-11 G-9 H-9 H-10 H-11 J-11 J-10 L-9 BIT# 25 26 27 28 29 30 31 32 33 34 35 36 BALL K-11 K-10 K-9 M-9 M-11 L-10 N-11 M-10 N-10 P-11 P-10 R-11 BIT# 37 38 39 40 41 42 43 44 45 46 47 48 BALL R-10 T-11 T-10 T-3 T-2 R-3 R-2 P-3 P-2 N-3 M-3 N-2 BIT# 49 50 51 52 53 54 55 56 57 58 59 60 BALL L-3 M-2 M-4 K-4 K-3 K-2 L-4 J-3 J-2 H-2 H-3 H-4 BIT# 61 62 63 64 65 66 67 BALL G-4 F-4 F-2 G-3 E-2 F-3 E-3
1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. Two RFU balls (#56 and #57) in the scan order, will read as a logic"0".
Data Sheet
24
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Boundary Scan
Table 10
Scan Pin Description DESCRIPTION Scan Shift: Capture the data input from the pad at logic LOW and shift the data on the chain at logic HIGH. Scan Clock: Not a true clock, could be a single pulse or series of pulses. All scan inputs will be referenced to rising edge of the scan clock Scan Output Scan Enable: Logic HIGH enables the device into scan mode and will be disabled at logic LOW. Must be tied to GND when not in use. Scan Output Enable: Enables (registered LOW) and disables (registered HIGH) SOUT data. This pin will be tied to VDD or GND through a resistor (typically 1K for normal operation. Tester needs to overdrive this pin to guarantee the required input logic level in scan mode.
PACKAGE SYMBOL NORMAL TYPE BALL FUNCTION V-9 F-9 SSH SCK RES CS Input Input
D-2 V-4
SOUT SEN
WDQS0 SEN
Output Input
A-9
SOE
MF
Input
Notes 1. When SEN is asserted, no commands are to be executed by the GDDR3. This applies both to user commands and manufacturing commands which may exist while RES is deasserted. 2. The Scan Function can be used right after bringing up VDD / VDDQ of the device. No initialization sequence of the device is required. After leaving the Scan Function it is required to run through the complete initialization sequence. 3. In Scan Mode all terminations for CMD/ADD and DQ, DM, RDQS and WDQS are switched off. 4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE's should be provided to top and bottom devices to access the scanned output. When either of the devices is in scan mode, SOE for the other device which is not in a scan will be disabled. Table 11 Scan DC Electrical Characteristics and Operating Conditions SYMBOL MIN MAX -- UNITS NOTES
1)2) 1) 2)
PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage -
VIH(DC) VIL(DC)
VREF+0.15
--
VREF-0.15 V
1) The parameter applies only when SEN is asserted. 2) All voltages referenced to GND.
Data Sheet
25
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Boundary Scan
SCK t SES
SEN Low SSH t SCS
SON Pins under Test
t SDS
t SDH
VALID
Don't Care
Figure 5
Scan Capture Timing
SCK t SES
SEN
t SCS
SSH t SCS SON
SON
Scan Out bit 0
Scan Out bit 1
Scan Out bit 2
Scan Out bit 3
t SAC
t SOH
Don't Care
Figure 6 Table 12 Clock
Scan Shift Timing Scan AC Electrical Characteristics SYMBOL MIN 40 20 20 14 14 10 10 MAX -- -- -- -- -- -- -- UNITS ns ns ns ns ns ns ns NOTES 1 1)2 1 1 1 1 1
PARAMETER/CONDITION Clock cycle time Scan Command Time Scan enable setup time Scan enable hold time Scan command setup time for SSH, SOE and SOUT Scan command hold time for SSH, SOE and SOUT Scan Capture Time Scan capture setup time Scan capture hold time Data Sheet 26
tSCK tSES tSEH tSCS tSCH tSDS tSDH
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Boundary Scan Table 12 Scan AC Electrical Characteristics SYMBOL MIN -- 1.5 MAX -- -- UNITS ns ns NOTES 1 1
PARAMETER/CONDITION Scan Shift Time Scan clock to valid scan output Scan clock to scan output hold Notes
tSAC tSOH
1. The parameter applies only when SEN is asserted. 2. Scan Enable should be issued earlier than other Scan Commands by 6 ns.
3.3
Scan Initilization
The initilization sequence for the boundary scan functionality depends on the intended SGRAM operation mode. There are two modes to distinguish. The first mode is the Stand-Alone mode. In the Stand-Alone mode the SGRAM is supposed to support the Boundary Scan functionality only, the user does not intend to operate the DRAM in its ordinary functionality after or prior to the entering of the Boundary Scan functionality. The purpose of the Stand-Alone mode could be a connectivity test at the manufacturing site. The second mode is the regular SGRAM functionality. With this common mode the boundary scan functionality can be enabled after the SGRAM has been initialized by the regular power-up and SGRAM initilization sequence. When the boundary scan functionality is left the regular SGRAM initialization sequence has to be re-iterated.
3.3.1
Scan initilization for Stand-Alone Mode
The SGRAM needs to follow the given sequence to support the boundary scan functionality in the Stand-Alone mode. There is no external clock for the whole sequence needed. Sequence Flow: 1.) external Voltages (VDD/VDDQ/VREF) need to be stable for 200us, SEN has to be kept low 2.) bring SEN up to high state to enter boundary scan functionality 3.) operate boundary scan functionality according to the scan features given in Chapter 3.2 4.) boundary scan can be exited by bringing SEN low or simply by switching power off The Scan initialization sequence for the Stand-Alone Mode is shown in Figure 7.
Data Sheet
27
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Boundary Scan
V DD V DDQ V REF tSDS tSDH
CLK/CLK# tSCS SSH [RES]
VALID tSCH
tSCS SEN
tSCH
tSES
SCK[CS#]
SOE[MF] tSCS SOUT[WDQS] tSDS Pins Under Test tSDH Scan Out Bit 0 VALID tSCS
T = 200s Boundary Scan Mode Power-up: VDD /VDDQ/VREF stable
Don't Care
Figure 7
Scan Initialization for Stand-Alone mode
3.3.2
Scan initilization in regular SGRAM operation
The initilization sequence of the boundary scan functionality in regular SGRAM operation has to follow the given sequence. Sequence Flow: 1.) external Voltages (VDD/VDDQ/VREF) need to be stable for 200us, RES has to be kept low, external clock has to be stable prior to RES goes high 2.) bring RES high and keep clock stable for 700tcks, CKE will be latched by rising RES edge, keep tATH/tATS 3.) bring SEN up to high state to enter boundary scan functionality 4.) operate boundary scan functionality accordingly to the scan features given in Chapter 3.2 5.) boundary scan can be exited by bringing SEN low 6.) wait tSN for bringing up RES, prior to bringing RES to high state external has to be stable 7.) after RES is at high state wait 700tck 8.) continue with regular initilization sequence (PRE-ALL, EMRS, MRS) The steps 1 and 2 are necessary to enable the termination for the command/address pins. They are part of the regular SGRAM initilization. They are required if the user wants to issue commands between to entering of the boundary scan functionality and the power-up sequence. The entering of the boundary scan mode is resetting the command/address termination values and all EMRS/MRS settings. Therefore they have to be initilized again after the boundary scan functionary has been left. Figure 8 shows the scan initilization sequence for regular SGRAM operation. Data Sheet 28 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Boundary Scan
V DD V DDQ V REF t SDS tSDH
CLK/CLK#
VALID t SCS t SCH
SSH[RES] t ATS t ATH t SDS t SDH t SCS t SCH
CKE
VALID
SEN SCK[#CS]
t SES
SOE[MF] t SCS SOUT[WDQS] t SDS Pins Under Test T = 200s 700tck t SDH Scan Out Bit 0 VALID t SCS
Power-up: VDD stable
RESET at power - up
Boundary Scan Mode
Don't Care
Figure 8
Scan Initialization Sequence within regular SGRAM Mode
Data Sheet
29
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Boundary Scan
3.3.3
Scan Exit Sequence
Figure 9 shows the Scan exit Sequence. This figure show the exiting of the boundary scan functionality in conjugation with the appended regular SGRAM initilization sequence to bring the SGRAM again in a well defined state.
stable clock CLK/ CLK# tRESL RES tATS tATH
Standard Power up sequence starting with PRE ALL
CKE tSN SEN
SOUT
invalid 700tck
Figure 9 Table 13 Parameter
Boundary Scan Exit Sequence Scan AC Electrical Parameters CAS latency Symbol Limit Values min max 20 20 Unit Notes
tRESL tSN
tRESL tSN
ns ns
Data Sheet
30
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4
4.1
Functional Description
Initialization
The HYB18H512321AF must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation or permanent damage to the device. The following sequence is highly recommended for Power-Up: 1. Apply power (VDD, VDDA, VDDQ, VREF). Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF. Maintain RES=L and CS=H to ensure that all the DQ ouputs will be in HiZ state, all active terminations off and the DLL off. All other pins may be undefined. 2. Maintain stable conditions for 200 s minimum for the to power up. 3. After clock is stable, set CKE to High or Low. After tATS minimum set RES to high. On the rising edge of RES, the CKE value is latched to determine the address and command bus termination value. If CKE is sampled LOW the address termination value is set to ZQ / 2. If CKE is sampled HIGH, the address and command bus termination is set to ZQ. 4. After tATH minimum, set CKE to high. 5. Wait a minimum of 700 cycles to calibrate and update the address and command termination impedances. Issue DESELECT on the command bus during these 700 cycles. 6. Apply a PRECHARGE ALL command, followed by an Extended Mode Register command after tRP is met and activate the DLL. 7. Issue an Mode Register Set command after tMRD is met to reset the DLL and define the operating parameters. 8. Wait 1000 cycles of clock input to lock the DLL. No Read command can be applied during this time. Since the impedance calibration is already completed, the DLL mimic circuitry can use the actual programmed driver impedance value. 9. Issue a PRECHARGE ALL command or issue 8 single bank PRECHARGE commands, one to each of the 8 banks to place the chip in an idle state. 10. Issue two or more AUTO REFRESH commands.
Data Sheet
31
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
VDD VDDQ VREF
t ATS tATH
RES CKE CLK# CLK Com . DM A0-A7, A9-A11 All Banks A 8
CODE CODE
DES
DES
PA
EMR
MRS
PA
ARF
ARF
ACT
CODE
CODE
RA All Banks RA
BA0 = H, BA0 = L, BA1 = L BA1 = L BA0, BA1 RDQS WDQS DQ RA
min. 200 s VDD and CLK stable
700 cycles
t
RP
t
MRD
t
MRD
t
RP
t RFC 1000cycles
t RFC
MRS: MRS command with DLL Reset EMR: EMRS command DES : Deselect
PA: PREALL command ARF: AUTO REFRESH command A.C.: Any command Don't Care
Figure 10
Power Up Sequence
Data Sheet
32
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.2 4.2.1
Programmable impedance output drivers and active terminations GDDR3 IO Driver and Termination
The is equipped with programmable impedance output buffers and active terminations. This allows the user to match the driver impedance to the system impedance. To adjust the impedance of DQ<0:31> and RDQS<0:3> , an external precision resistor (ZQ) is connected between the ZQ pin and VSS. The value of the resistor must be six times the value of the desired impedance. For example, a 240 resistor is required for an output impedance of 40 . The range of ZQ is 210 to 270 , giving an output impedance range of 35 to 45 (one sixth the value of ZQ within 10%). The value of ZQ is used to calibrate the internal DQ termination resistors of DQ<0:31>, WDQS<0:3> and DM<0:3>. The two termination values that are selectable using EMRS[3:2] are ZQ / 4 and ZQ / 2. The value of ZQ is also used to calibrate the internal address command termination resistors. The inputs terminated in this manner are A<0:11>, CKE, CS, RAS, CAS, WE. The two termination values that are selectable upon power up (CKE latched LOW to HIGH transition of RES) are ZQ/2 and ZQ. RES, MF, CLK and CLK are not internally terminated. If no resistance is connected to ZQ, an internal default value of 240 will be used. In this case, no calibration will be performed.
VDDQ ZQ/4 or ZQ/2 Terminator when receiving
Read to other Rank
Output Data Read Data Enable DQ
ZQ/6 Driver when transmitting
VSSQ
Figure 11 Table 14 Parameter
Output Driver simplified schematic Range of external resistance ZQ Symbol ZQ min 210 nom 240 max 270 Units Notes
External resistance value Table 15 Ball CLK, CLK, RDQS<0:3>, ZQ, RES, MF
Termination Types and Activation Termination type No termination Add / CMDs DQ DQ Always ON Always ON CMD bus snooping Termination activation
CKE, CS, RAS, CAS, WE, BA0 - BA2, A<0:11> DM<0:3>, WDQS<0:3>, DQ<0:31>
Data Sheet
33
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.2.2
Self Calibration for Driver and Termination
The ouput impedance is updated during all AREF commands. These updates are used to compensate for variations in supply voltage and temperature. Impedance updates do not affect device operation. No activity on the Address, command and data bus is allowed during a minimum Keep Out time tKO after the Autorefresh command has been issued.
CLK# CLK
Com.
ARF
NOP
Add.
DQ
t KO
ARF:
Autorefresh
Don't Care Keep Out time
Figure 12
Termination update Keep Out time after Autorefresh command
To guarantee optimum driver impedance after power-up, the needs 700 cycles after the clock is applied and stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 700 cycles, but optimal output impedance will not be guaranteed. The GDDR3 Graphics RAM proceeds in the following manner for Self Calibration: The PMOS device is calibrated against the external ZQ resistor value. First one PMOS leg is calibrated against ZQ. The number of legs used for the terminators ( DQ and ADD/CMD) and the PMOS driver is represented in Table 16. Next, one NMOS leg is calibrated against the already calibrated PMOS leg. The NMOS driver uses 6 NMOS legs.
Data Sheet
34
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
Table 16
Number of Legs used for Terminator and Driver Self Calibration Termination CKE (at RES) Number of Legs Notes 2 1 0 4 2 6 6
1)
Terminator
ADD / CMD
0 1 EMRS[3:2]
ZQ/2 ZQ Disabled ZQ/4 ZQ/2 ZQ/6 ZQ/6
DQ
00 10 11
Driver
PMOS NMOS
1) EMRS[3:2] = 00 disables the ADD and CMD terminations as well.
Figure 13 represents a simplified schematic of the calibration circuits. First, the strength control bits are adjusted in such a way that the VDDQ voltage is divided equaly between the PMOS device and the ZQ resistor. The best bit pattern will cause the comparator to switch the PMOS Match signal output value. In a second step, the NFET is calibrated against the already calibrated PFET. In the same manner, the best control bit combination will cause the comparator to switch the NMOS Match signal output value.
VDDQ
VDDQ
Strength Control [2:0]
VSSQ
NMOS Calibration
PMOS Calibration
Match VDDQ / 2
ZQ Match VDDQ / 2 VSSQ
Strength Control [2:0]
VSSQ
Figure 13
Self Calibration of PMOS and NMOS Legs
Data Sheet
35
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.2.3
Dynamic Switching of DQ terminations
The GDDR3 Graphics RAM will disable its data terminators when a READ or DTERDIS command is detected. The terminators are disabled starting at CL - 1 Clocks after the READ / DTERDIS command is detected and the duration is 4 clocks. In a two rank system, both devices will snoop the bus for a READ / DTERDIS command to either device and both will disable their terminators if a READ / DTERDIS command is detected. The address and command terminators are always enabled.
0 CLK# CLK Com . 1 2 5 6 7 8 9 10 11
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/C
CAS latency = 7 RDQS
DQ D0 D1 D2 D3
DQ Termination
Data Terminations are disabled
Dx:
Data from B / C
B / C: Bank / Column address RD: N/D: READ NOP or Deselect
Com.: Command Addr.: Address B / C Don't Care
Figure 14
ODT Disable Timing during a READ command
4.2.4
Output impedance and Termination DC Electrical Characteristics
The Driver and Termination impedances are determined by applying VDDQ/2 nominal at the corresponding input / output and by measuring the current flowing into or out of the device. VDDQ is set to the nominal value.
IOH is the current flowing out of DQ when the Pull-Up transistor is activated and the DQ termination disabled. IOLis the current flowing into DQ when the Pull-Down transistor is activated and the DQ termination disabled. ITCAH(ZQ) is the current flowing out of the Termination of Commands and Addresses for a ZQ termination value.
Table 17 Parameter ZQ Value DC Electrical Characteristics Nom. 240 min max 25.0 25.0 4.2 mA mA mA
1) 1) 1)
Unit
Notes
IOH IOL ITCAH(ZQ)
ZQ/6 ZQ/6 ZQ
20.5 20.5 3.4
1) Measurement performed with VDDQ (nominal) and by applying VDDQ/2 at the corresponding Input / Output. 0 C Tc 85
Data Sheet
36
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.3
CLK#
Extended Mode Register Set Command (EMRS)
The Extended Mode Register is used to set the output driver impedance value, the termination impedance value, the Write Recovery time value for Write with Autoprecharge. It is used as well to enable/disable the DLL, to issue the Vendor ID and to enable/disable the Low Power mode. There is no default value for the Extended Mode Register. Therefore it must be written after power up to operate the GDDR3 Graphics RAM. The Extended Mode Register can be programmed by performing a normal Mode Register Set operation and setting the BA0 bit to HIGH. All other bits of the EMR register are reserved and should be set to LOW. The Extended Mode Register must be loaded when all banks are idle and no burst are in progress. The controller must wait the specified time tMRD before initiating any subsequent operation (Figure 16). The timing of the EMRS command operation is equivalent to the timing of the MRS command operation.
CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
COD
BA0
1
COD: Code to be loaded into the register
BA1, BA2
0
Don't Care
Figure 15
Extended Mode Register Set Command
BA2 BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
1
LP
V
RFU
WR
DLL
WR
Rtt
Data Z
A11
SelfRefresh 32ms 8ms
A6
DLL Enable Enable Disable
A1
A0
Output Driver Impedance Autocal 35 40 45
0 1
0 1
0 0 1 1
0 1 0 1
A10 0 1
Vendor ID Off On
A7 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
WR 11 4 0 5 0 6 1 7 8 9 10 1 1 ZQ / 2 (Default)
2)
A3
A2 0 1 0
Termination ODT disabled RFU ZQ / 4
Figure 16
Extended Mode Register Bitmap option implemented in the device) or no action is taken by the device (if option not implemented). 5. WR (write recovery time for autoprecharge) in clock cycles is calculated by dividing tWR (in ns) and rounding up to the next integer (WR[cycles] = tWR[ns] / tCK[ns]). The mode register must be programmed to this value. 37 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
1. These settings are for debugging purposes only. 2. Default termination values at Power Up. 3. The ODT disable function disables all terminators on the device. 4. If the user activates bits in the extended mode register in an optional field, either the optional field is activated (if Data Sheet
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
CLK# CLK
Command
PA
NOP t RP
EMRS
NOP t MRD
NOP
A.C.
A.C.:
Any command
EMRS: Extended MRS command PA: PREALL command
Don't Care
Figure 17
Extended Mode Register Set Timing
4.3.1
DLL enable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is enabled automatically). Anytime the DLL is enabled, 1000 cycles must occur before a READ command can be issued.
4.3.2
WR
The WR parameter is programmed using the register bits A4, A5 and A7. This integer parameter defines as a number of clock cycles the Write Recovery time in a Write with Autoprecharge operation. The following inequality has to be complied with : WR * tCK tWR, where tCK is the clock cycle time.
4.3.3
Termination Rtt
The data termination, Rtt, is used to set the value of the internal termination resistors. The GDDR3 DRAM supports ZQ / 4 and ZQ / 2 termination values. The termination may also be disabled for testing and other purposes.
4.3.4
Output Driver Impedance
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance. When the autocalibration is used, the output driver impedance is set nominally to ZQ / 6.
4.3.5
Low Power
When the Low Power extended mode register is set, the device changes its internal self-refresh rate from 32 ms to 8 ms. This allows self-refresh operation at higher temperatures for mobile applications.
Data Sheet
38
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.3.6
Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set to 1 and bits A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3 DRAM will provide the Infineon vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will be driven onto the DQ bus after tRIDon following the EMRS command that sets A10 to 1. The Vendor Code and Revision ID will be driven on DQ[7:0] until a new EMRS command is issued with A10 set back to 0. After tRDoff following the second EMRS command, the data bus is driven back to HIGH. This second EMRS command must be issued before initiating any subsequent operation. Violating this requirement will result in unspecified operation. Table 18 DQ[7:4] 0000 Revision ID and Vendor Code Infineon Vendor Code DQ[3:0] 0010
Revision Identification
Note: Please refer to Revision Release Note for Revision ID value
0 CLK# CLK Com.
EMRS
1
2
3
4
5
6
7
8
9
10
N/D
N/D
N/D
N/D
N/D
EMRS
N/D
N/D
N/D
N/D
A[9:0], A11
Add
Add
A10 t RDQS RIDon t RIDoff
DQ[7:0]
Vendor Code and Revision ID
EMRS: Extended Mode Register Set Command Add: Address N/D: NOP or Deselect Don't Care
Figure 18
Timing of Vendor Code and Revision ID Generation on DQ[7:0]
Data Sheet
39
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
Functional Description
www..c
4.4
CLK# CLK
Mode Register Set Command (MRS)
The mode register stores the data for controlling the operating modes of the memory. It programs CAS latency, test mode, DLL Reset and the value of the write latency. There is no default value for the mode register; therefore it must be written after power up to operate the . During a Mode Register Set command the address inputs are sampled and stored in the mode register.
CKE
CS#
tMRD must be met before any command can be issued
RAS#
to the Graphics SDRAM. The Mode Register contents can only be set or changed when the Graphics SDRAM is in idle state.
CAS#
WE#
A0-A11
COD
BA0
0
COD: Code to be loaded into the register
BA1, BA2
0
Don't Care
Figure 19
Mode Register Set Command
BA2
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
WL
DLL
TM
CAS Latency
BT
BL
Burst Length Write Latency
A11 0 1 A10 1 0 all others A9 1 0 WL 3 4 RFU A7 0 1 A2 A1 1 1 all others A0 0 1 BL 4 8 RFU
Testmode
mode Normal Testmode 0 0
CAS Latency DLL Reset
A8 0 1 DLL Reset No Yes A6 0 0 0 0 1 A5 0 0 1 1 1 all others A4 0 1 0 1 1 Latency A3 8 0 9 1 10 11 7 RFU RFU sequential
Burst Type
BT
Note: 1) The DLL Reset command is self-clearing
Figure 20
Mode Register Bitmap
Data Sheet
40
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
CLK# CLK
Com.
PA
NOP
MRS
NOP
NOP
A.C.
NOP
RD
t RP
t MRD tMRDR
MRS: MRS command PA: PREALL command A.C.: Any other command as READ RD: READ command Don't Care
Figure 21
Mode Register Set Timing
4.4.1
Burst length
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length of 4 and 8. This value must be programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block if a boundary is reached. The starting location within this block is determined by the two least significant bits A0 and A1 which are set internally to the fixed value of zero each. Reserved states should not be used, as unknow operation or incompatibility with future versions may result.
4.4.2
Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3) . This device does not support the burst interleave mode. Table 19 Burst Definition Starting Column Adress A2 4 8 -- 0 1 A1 X X X A0 X X X 0-1-2-3 0-1-2-3-4-5-6-7 4-5-6-7-0-1-2-3 Order of Accesses within a Burst (Type = sequential) Burst Length
The value applied at the balls A0 and A1 for the column address is "Don't care"
4.4.3
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data as shown on Figure 38. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Data Sheet
41
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.4.4
Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data as shown in Figure 28.
4.4.5
Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits A0-A6 and A8-A11 set to the desired value.
4.4.6
DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits A0-A7 and A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns automatically in the normal mode of operations once the DLL reset is completed.
Data Sheet
42
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.5
Bank / Row Activation (ACT)
CLK# CLK
Before a READ or WRITE command can be issued to a bank, a row in that bank must be opened. This is accomplished via the ACT command, which selects both the bank and the row to be activated. After opening a row by issuing an ACT command, a READ or WRITE command may be issued after tRCD to that row. A subsequent ACT command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACT commands to the same bank is defined by tRC. A subsequent ACT command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACT commands to different banks is defined by tRRD.
RA: Row Address BA: Bank Address
CKE
CS#
RAS#
CAS#
WE#
A0-A11
RA
BA0-BA2
BA
There is a minimum time tRAS between opening and closing a row.
Don't Care
Figure 22
CLK# CLK Com. A0-A11 BA0-BA2
Activating a specific row
ACT Row B.Y t RCD
R/W Col B.Y t RAS
PRE A8 B.Y
ACT Row B.Y
ACT Row B.X
Row: Row Address Col: Column Address B.X: Bank X B.Y: Bank Y R/W: READ or WRITE command PRE: PRECHARGE command ACT: ACTIVATE command
t RC
t RRD
Don't Care
Figure 23
Bank Activating Timing
For eight bank GDDR3 devices, there may be a need to limit the number of activates in a rolling window to ensure that the instantaneous current supplying capability of the devices is not exceeded. To reflect the true capability of the DRAM instantaneous current supply, the parameter tFAW (four activate window) is defined. No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up the next integer value. As an example of the rolling window, if (tFAW / tCK) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued in clocks n+1 through n+9.
Data Sheet
43
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
CLK# CLK ACT tRRD ACT tRRD tFAW t FAW +3*tRRD ACT tRRD ACT ACT tRRD ACT tRRD ACT tRRD ACT
ACT: ACTIVATE command Don't Care
Figure 24
Four Window Active tFAW
t CK
t CH
t CL
CLK# CLK t IPW CMD, ADDR, CKE t IS t IH
Don't Care
Figure 25
Clock, CKE and Command/Address Timings
Setup and Hold Timing for CKE is equal to CMD and ADDR Setup and Hold Timing.
Data Sheet
44
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.6 4.6.1
Writes (WR) Write - Basic Information
CLK# CLK
CKE
with Autoprecharge can be programmed in the Mode Register. Choosing high values for WR will prevent the chip to delay the internal Autoprecharge in order to meet tRAS(min). During WR bursts data will be registered with the edges of WDQS. The write latency can be programmed during Extended Mode Register Set. The first valid data is registered with the first valid rising edge of WDQS following the WR command. The externally provided WDQS must switch from HIGH to LOW at the beginning of the preamble. There is also a postamble requirement before the WDQS returns to HIGH. The WDQS signal can only transition when data is applied at the chip input and during pre- and postambles.
CS#
RAS#
CAS#
WE#
tDQSS is the time between WR command and first valid
A2-A7, A9 CA
A0, A1 A10-A11
A8
AP
AP: AutoPrecharge CA: Column Address BA: Bank Address
rising edge of WDQS. Nominal case is when WDQS edges are aligned with edges of external CLK. Minimum and maximum values of tDQSS define early and late WDQS operation. Any input data will be ignored before the first valid rising WDQS transition. tDQSL and tDQSH define the width of low and high phase of WDQS. The sum of tDQSL and tDQSH has to be tCK. Back to back WR commands are possible and produce a continuous flow of input data. There must be one NOP cycle between two back to back WR commands. Any WR burst may be followed by a subsequent RD command. Figure 32 shows the timing requirements for a WR followed by a RD. A WR may also be followed by a PRE command to the same bank. tWR has to be met as shown in Figure 35. Setup and hold time for incoming DQs and DMs relative to the WDQS edges are specified as tDS and tDH. DQ and DM input pulse width for each input is defined as tDIPW. The input data is masked if the corresponding DM signal is high. All timing parameters are defined with graphics DRAM terminations on.
BA0-BA2
BA
Don't Care
Figure 26
Write Command
Write bursts are initiated with a WR command, as shown in Figure 26. The column and bank addresses are provided with the WR command, and Auto Precharge is either enabled or disabled for that access. The length of the burst initiated with a WR command is four or eight depending on the mode register setting. There is no interruption of WR bursts. The two least significant address bits A0 and A1 are 'Don't Care'. For WR commands with Autoprecharge the row being accessed is precharged tWR/A after the completion of the burst. If tRAS(min) is violated the begin of the internal Autoprecharge will be performed one cycle after tRAS(min) is met. WR, the write recovery time for write Table 20 WDQS WDQS0 WDQS1 WDQS2 WDQS3 Data Sheet Mapping of WDQS and DM Signals
Data mask signal DM0 DM1 DM2 DM3 45
Controlled DQs DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
CLK# CLK nominal WDQS tDQSS tWPRE Preamble WDQS tDQSS nominal tDIPW DQ D0 tDS Data masked min(tDQSS) D1 tDH tDIPW Data masked D2 D3 tDS tDQSH tDH tDQSL tDQSH tDS tDH tWPST Postamble
DMx
early WDQS WDQS late WDQS WDQS
max(tDQSS)
Don't Care
DMx: Represents one DM line
Figure 27
Basic Write Burst / DM Timing
Note: WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
46
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.6.2
Write - Basic Sequence
0 CLK# CLK Com. WR N/D DES DES DES DES DES DES DES 1 2 3 4 5 6 7 8
Addr.
B/C
WL = 3 WDQS
DQ
D0
D1
D2
D3
WL = 4 WDQS
DQ
D0
D1
D2
D3
Com.
WR
N/D
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Addr.
B/C
WL = 3
DQ
D0
D1
D2
D3
WL = 4 WDQS
DQ B / C: Bank / Column address WR: WRITE NOP: No Operation
D0
D1
D2
D3 Addr.: Address B / C D#: Data to B / C WL: Write Latency Don't Care
DES: Deselect N/P: NOP or DES Com.: Command
Figure 28 1. 2. 3. 4.
Write Basic Sequence
Shown with nominal value of tDQSS. WDQS can only transition when data is applied at the chip input and during pre- and postambles. When NOPs are applied on the command bus, the WDQS and the DQ busses remain stable High. When DESs are applied on the command bus, the status of the WDQS and DQ busses is unknown.
Data Sheet
47
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.6.3 4.6.3.1
Write - Consecutive Bursts Gapless Bursts
0 1 2 3 4 5 6 7 8 9
CLK# CLK
Com.
WR
N/D
WR
N/D
DES
DES
DES
DES
DES
DES
Addr.
B/Cx
B/Cy
WL = 3
WDQS
DQ
Dx0
Dx1
Dx2
Dx3
Dy0
Dy1
Dy2
Dy3
WL = 4
WDQS
DQ
Dx0
Dx1
Dx2
Dx3
Dy0
Dy1
Dy2
Dy3
WR: DES: N/D:
WRITE Deselect NOP / Deselect
B / Cx: Bank / Column address x B / Cy: Bank / Column address y WL: Write Latency Don't Care
Dx#: Data to B / Cx Dy#: Data to B / Cy Com.: Command Addr.: Address B / C
Figure 29
Gapless Write Bursts
1. Shown with nominal value of tDQSS. 2. The second WR command may be either for the same bank or another bank. 3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
48
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.6.3.2
0 CLK# CLK Com .
Bursts with Gaps
1 2 3 4 5 6 7 8 9 10
WR
N/D
N/D
WR
N/D
DES
DES
DES
DES
DES
DES
Addr.
B/Cx
B/Cy
WL = 3 WDQS
DQ
Dx0
Dx1
Dx2
Dx3
Dy0
Dy1
Dy2
Dy3
WL = 4 WDQS
DQ
Dx0
Dx1
Dx2
Dx3
Dy0
Dy1
Dy2
Dy3
Com.: Command Addr.: Address B / C WL: Write Latency DES: Deselect N/D: NOP / Deselect Don't Care
B / Cx: Bank / Column address x B / Cy: Bank / Column address y WR: WRITE Dx#: Data to B / Cx Dy#: Data to B / Cy
Figure 30
Consecutive Write Bursts with Gaps
1. Shown with nominal value of tDQSS. 2. The second WR command may be either for the same bank or another bank. 3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
49
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.6.4
0 CLK# CLK
Write with Autoprecharge
1 2 3 4 5 6 7 8 9 10 11
Com.
WR/A
N/D
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
A9, A7-A2
B/C
A8
WL = 3 WDQS
tWR/A =4
tRP DQ D0 D1 D2 D3
tRAS MIN satisfied WL = 4 WDQS t WR/A =4
Begin of Autoprecharge
tRP DQ D0 D1 D2 D3
tRAS MIN satisfied
Com.: Command Addr.: Address B / C WL: Write Latency Don't Care D#: DES: N/D:
Begin of Autoprecharge
B / C: Bank / Column address WR/A: WRITE with auto-precharge Data to B / C Deselect NOP or Deselect
Figure 31 1. 2. 3. 4.
Write with Autoprecharge
Shown with nominal value of tDQSS. tWR/A starts at the first rising edge of CLK after the last valid edge of WDQS. tRP starts after tWR/A has been expired. When issuing a WR/A command please consider that the tRAS requirement also must be met at the beginning of tRP. 5. tWR/A * tCYC tWR. 6. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
50
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.6.5
Write followed by Read
0 CLK# CLK 1 2 3 4 5 6 7 8 9
WR
N/D
DES
DES
DES
DES
DES
DES
RD
N/D
B/C
B/C
WL = 3
t WTR
WDQS
DQ
D0
D1
D2
D3
WR
N/D
DES
DES
DES
DES
DES
DES
DES
RD
B/C
B/C
WL = 4
t WTR
WDQS
DQ
D0
D1
D2
D3
D#: Data to B / Cx Com.: Command Addr.: Address B / C WL: Write Latency Don't Care
B / C: WR: RD: DES: N/D:
Bank / Column address WRITE READ Deselect NOP / Deselect
Figure 32
Write followed by Read
1. Shown with nominal value of tDQSS. 2. The RD command may be either for the same bank or another bank. 3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
51
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.6.6
Write followed by DTERDIS
0 1 2 3 4 5 6 7 8 9 10
CLK# CLK
WR
DTD
DES
DES
DES
DES
DES
DES
DES
DES
DES
B/C CL = 7 WL = 3 WDQS
DQ
D0
D1
D2
D3
WR
N/D
DTD
DES
DES
DES
DES
DES
DES
DES
DES
B/C CL = 7 WL = 4 WDQS
DQ
D0
D1
D2
D3
B / C: Bank / Column address WR: DTD: D#: WRITE DTERDIS Data to B / Cx
WL: CL: DES: N/D:
Write Latency CAS Latency Deselect NOP or Deselect Don't Care Data Termination Off
Com.: Command Addr.: Address B / C
Figure 33
Write Command followed by DTERDIS
1. Shown with nominal value of tDQSS. 2. WDQS can only transition when data is applied at the chip input and during pre- and postambles. 3. A margin of one clock has been introduced in order to make sure that the data termination are still on when the last Write data reaches the memory. 4. The minimum distance between Write and DTERDIS is one clock.
Data Sheet
52
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.6.7
Write with Autoprecharge followed by Read / Read with Autoprecharge
0 1 2 3 4 5 6 7 8 9 10
CLK# CLK Com. WR/A N/D DES DES DES DES DES DES DES RD RD/A DES
A9, A2-A7
B/C
B/C
A8 tWTR tWR/A
WL = 3 WDQS
tRP
DQ
D0
D1
D2
D3
Begin of Autoprecharge
Com.
WR/A
N/D
DES
DES
DES
DES
DES
DES
DES
DES
RD RD/A
A9, A2-A7
B/C
B/C
A8 tWTR tWR/A
WL = 4 WDQS
tRP
DQ
D0
D1
D2
D3
Begin of Autoprecharge B / C: Bank / Column address WR/A: WRITE with Autoprecharge RD RD/A: READ or READ with Autoprecharge D#: Data to B / Cx DES: Deselect N/D: NOP or Deselect
Com.: Command Addr.: Address B / C WL: Write Latency Don't Care 0: RD, 1: RD/A
Figure 34 1. 2. 3. 4.
Write with Autoprecharge followed by Read or Read with Autoprecharge on another bank.
Shown with nominal value of tDQSS. The RD command is only allowed for another activated bank. tWR/A is set to 4 in this example. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
53
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.6.8
0 CLK# CLK
Write followed by Precharge on same bank.
1 2 3 4 5 6 7 8 9 10
WR
N/D
DES
DES
DES
DES
DES
DES
DES
PRE
DES
B/C
B
WL = 3 WDQS
tWR
t RP
DQ
D0
D1
D2
D3
WR
N/D
DES
DES
DES
DES
DES
DES
DES
DES
PRE
B/C
B
WL = 4 WDQS
t WR
tRP
DQ
D0
D1
D2
D3
N/D: NOP or Deselect DES: Deselect Com.: Command Addr.: Address B / C WL: Write Latency Don't Care
B / C: Bank / Column address WR: WRITE PRE: PRECHARGE Dx#: Data to B / Cx Dy#: Data to B / Cy
Figure 35 1. 2. 3. 4.
Write followed by Precharge on same Bank
Shown with nominal value of tDQSS. WR and PRE commands are to same bank. tRAS requirement must also be met before issuing PRE command. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
54
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.7 4.7.1
Reads (RD) Read - Basic Information
CLK# CLK
its first rising edge (RD preamble tRPRE). After the last falling edge of RDQS a postamble of tRPST is performed.
tAC is the time between the positive edge of CLK and
CKE
CS#
RAS#
CAS#
WE#
A2-A7, A9
CA
A0, A1 A10-A11
the appearance of the corresponding driven read data. The skew between RDQS and the crossing point of CLK/CLK is specified as tDQSCK. tAC and tDQSCK are defined relatively to the positive edge of CLK. tDQSQ is the skew between a RDQS edge and the last valid data edge belonging to the RDQS edge. tDQSQ is derived at each RDQS edge and begins with RDQS transition and ends with the last valid transition of DQs. tQHS is the data hold skew factor and tQH is the time from the first valid rising edge of RDQS to the first conforming DQ going non-valid and it depends on tHP and tQHS. tHP is the minimum of tCL and tCH. tQHS is effectively the time from the first data transition (before RDQS) to the RDQS transition. The data valid window is derived for each RDQS transition and is defined as tQH minus tDQSQ. After completion of a burst, assuming no other commands have been initiated, data will go HIGH and RDQS will go HIGH. Back to back RD commands are possible producing a continuous flow of output data. There has to be one NOP cycle between back to back RD commands. Any RD burst may be followed by a subsequent WR command. The minimum required number of NOP commands between the RD command and the WR command (tRTW) depends on the programmed Read latency and the programmed Write latency
A8
AP
AP: AutoPrecharge CA: Column Address BA: Bank Address
BA0-BA2
BA
Don't Care
Figure 36
Read Command
Read bursts are initiated with a RD command, as shown in Figure 36. The column and bank addresses are provided with the RD command and Autoprecharge is either enabled or disabled for that access. The length of the burst initiated with a RD command is 4 or 8. There is no interruption of RD bursts. The two least significant start address bits are 'Don't Care'. If Autoprecharge is enabled, the row being accessed will start precharge at the completion of the burst. The begin of the internal Autoprecharge will always be one cycle after tRAS(min) is met. During RD bursts the memory device drives the read data edge aligned with the RDQS signal which is also driven by the memory. After a programmable CAS latency of 7, 8. 9 or 10 the data is driven to the controller. RDQS leaves HIGH state one cycle before
tRTW(min)= (CL+4-WL).
Chapter 4.7.7 shows the timing requirements for RD followed by a WR with some combinations of CL and WL. A RD may also be followed by a PRE command. Since no interruption of bursts is allowed the minimum time between a RD command and a PRE is two clock cycles as shown in Chapter 4.7.8. All timing parameters are defined with controller terminations on.
Data Sheet
55
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
tCH CLK# CLK RDQS
tCL
tCK
tHP
tDQSCK
Preamble tRPRE DQ (first data valid) DQ (last data valid) tAC All DQs collectively D0 tDQSQ tQH tLZ tQHS D1 data valid window D2 tDQSQ D0 D0 D1 D1 D2 D2 D3
Postamble tRPST
D3
D3
Don't Care Hi-Z : Not driven by DDRIII SGRAM
tHZ
Figure 37
Basic Read Burst Timing 2. The GDDR3 SGRAM drives the data bus HIGH one cycle after the last data driven on the bus before switching the termination on again.
1. The GDDR3 SGRAM switches off the DQ terminations one cycle before data appears on the bus and drives the data bus HIGH.
Data Sheet
56
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.7.2
0 CLK# CLK
Read - Basic Sequence
1 2 3 6 7 8 9 10 11
Com.
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/C
CAS latency = 7
RDQS
DQ
D0
D1
D2
D3
CAS latency = 8
RDQS
DQ D0 D1 D2 D3
B / C: Dx: Com.: Addr.:
Bank / Column address Data from B / C Command Address B / C
RD: N/D:
READ Nop or Deselect
Don't Care DQs : Terminations off RDQS : Not driven
Figure 38
Read Burst
1. Shown with nominal tAC and tDQSQ. 2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data.
Data Sheet
57
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.7.3 4.7.3.1
0 CLK# CLK
Consecutive Read Bursts Gapless Bursts
1 2 3 6 7 8 9 10 11 12 13
Com.
RD
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/Cx
B/Cy
CAS latency = 7
RDQS
DQ
Dx0
Dx1
Dx2
Dx3
Dy0
Dy1
Dy2
Dy3
CAS latency = 8
RDQS
DQ
Dx0
Dx1
Dx2
Dx3
Dy0
Dy1
Dy2
Dy3
B / Cx: Bank / Column address x B / Cy: Bank / Column address y Dx#: Dy#: Data from B / Cx Data from B / Cy
RD: N/D:
READ NOP or Deselect Don't Care DQs : Terminations off RDQS : Not driven
Com.: Command Addr.: Address B / C
Figure 39 1. 2. 3. 4.
Gapless Consecutive Read Bursts
The second RD command may be either for the same bank or another bank. Shown with nominal tAC and tDQSQ. Example applies only when READ commands are issued to same device. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 5. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data.
Data Sheet
58
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.7.4
0 CLK# CLK
Bursts with Gaps
1 2 3 6 7 8 9 10 11 12
Com.
RD
N/D
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/Cx
B/Cy
CAS latency = 7
RDQS
DQ
Dx0
Dx1
Dx2
Dx3
Dy0
Dy1
Dy2
Dy3
CAS latency = 8
RDQS
DQ
Dx0
Dx1
Dx2
Dx3
Dy0
Dy1
Dy2
B / Cx: B / Cy: RD: Dx#: Dy#: Com.: Addr.:
Bank / Column address x Bank / Column address y READ Data from B / Cx Data from B / Cy Command Address B / C
Don't Care DQs : Terminations off RDQS : Not driven
Figure 40
Consecutive Read Bursts with Gaps
1. The second RD command may be either for the same bank or another bank. 2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data.
Data Sheet
59
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.7.5
0 CLK# CLK Com. RD
Read followed by DTERDIS
1 2 3 6 7 8 9 10 12 13 14 15 16
N/D
N/D
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/Cx CAS latency = 7
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
0 CLK# CLK Com. RD
1
2
3
6
7
8
9
10
13
14
15
16
17
N/D
N/D
N/D
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/Cx CAS latency = 7
RDQS
DQ
Dx0 Dx1 Dx2 Dx3 B / Cx: Dx#: Com.: Addr.: Bank / Column address x Data from B / Cx Command Address B / C RD: DTD: DES: N/D: READ DTERDIS Deselect NOP or Deselect Don't Care DQs : Terminations off RDQS : Not driven
Figure 41
Read Command followed by DTERDIS
1. At least 3 NOPs are required between a READ command and a DTERDIS command in order to avoid contention on the RDQS bus in a 2 rank system. 2. CAS Latency 7 is used as an example. 3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4 clocks. 4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case, RDQS would be driven by the second Graphics DRAM.
Data Sheet
60
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
Functional Description
www.DataShee
4.7.6
Read with Autoprecharge
0 CLK# CLK
1
2
3
6
7
8
9
10
Com.
RD/A
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
A9, A7-A2
B/C
A8
CAS latency = 7 RDQS
DQ
D0
D1
D2
D3
CAS latency = 8
RDQS
DQ BL / 2 tRP Begin of Autoprecharge B / C: RD/A: Dx: Com.: Addr.:
D0
D1
D2
D3
Bank / Column address READ with auto-precharge Data from B / C Command Address B / C
N/D: NOP or Deselect Don't Care DQs : Terminations off RDQS : Not driven
Figure 42
Read with Autoprecharge
1. When issuing a RD/A command , the tRAS requirement must be met at the beginning of Autoprecharge 2. Shown with nominal tAC and tDQSQ 3. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 4. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data. 5. tRAS Lockout support.
Data Sheet
61
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.7.7
0 CLK# CLK Com.
Read followed by Write
1 2 3 6 7 8 9 10 11 12 13
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
Addr.
B/Cr CAS latency = 7 tRTW
B/Cw
Write latency = 3
RDQS
WDQS
DQ
D0r D1r D2r D3r
D0w D1w D2w D3w
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cr CAS latency = 8 tRTW RDQS
B/Cw
Write latency = 4
WDQS
DQ
D0r D1r D2r D3r
D0w D1w D2w
B / Cr: Bank / Column address for READ B / Cw: Bank / Column address for WRITE RD: READ WR: WRITE DES: Deselect
Dxr: READ Data from B / C Dxw: WRITE Data from B / C Com.: Command Addr.: Address B / C
Don't Care DQs : Terminations off RDQS : Not driven
Figure 43
Read followed by Write
1. Shown with nominal tAC, tDQSQ and tDQSS 2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data 4. WDQS can only transition when data is applied at the chip input and during pre- and postambles. 5. The Write command may be either on the same bank or on another bank.
Data Sheet
62
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www.DataShee
Functional Description
4.7.8
Read followed by Precharge on the same Bank
0 1 2 3 6 7 8 9 10
CLK# CLK
Com.
RD
N/D
PRE
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/C
CAS latency = 7
RDQS
DQ
D0
D1
D2
D3
CAS latency = 8
RDQS
DQ
D0
D1
D2
D3
t RP Com.: Command Addr.: Address B / C
B / C: Bank / Column address RD: READ PRE: PRECHARGE Dx: Data from B / C N/D: NOP or Deselect
Don't Care DQs : Terminations off RDQS : Not driven
Figure 44 1. 2. 3. 4.
Read followed by Precharge on the same bank
tRAS requirement must also be met before issuing PRE command
RD and PRE commands are applied to the same bank. Shown with nominal tAC and tDQSQ RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS.
Data Sheet
63
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.8
Data Termination Disable (DTERDIS)
CLK# CLK
CKE
The Data Termination Disable command is detected by the device by snooping the bus for Read commands when CS is high. The terminators are disabled starting at CL - 1 clocks after the DTERDIS command is detected and the duration is 4 clocks. The command and address terminators are always enabled. DTERDIS may only be applied to the GDDR3 Graphics memory if it is not in the Power Down or in the Self Refresh state. The timing relationship between DTERDIS and other commands is defined by the constraint to avoid contention on the RDQS bus (i.e Read to DTERDIS transistion) or the necessity to have a defined termination on the data bus during Write (i.e. Write to DTERDIS transition). ACT and PRE/PREALL may be applied at any time before or after a DTERDIS command.
CS#
RAS#
CAS#
WE#
A2-A7, A9
A0, A1 A10-A11
A8
AP: AutoPrecharge
BA0-BA2
Don't Care
Figure 45
0 CLK# CLK
Data Terminal Disable Command
1 2 3 6 7 8 9 10 11
Com.
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
CAS latency = 7
DQ Termination
Data Terminations are disabled
DTD: DTERDIS Com.: Command Addr.: Address B / C
Don't Care N/D : NOP or Deselec
Figure 46
DTERDIS Timing
Data Sheet
64
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.8.1
0 CLK# CLK
DTERDIS followed by DTERDIS
1 2 3 6 7 8 9 10 11 12 13 14 15
Com.
DTD
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
CAS latency = 7
RDQS
DQ
0 CLK# CLK
3
4
5
6
7
8
9
10
11
12
13
14
15
Com.
DTD
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr. CAS latency = 7
RDQS
DQ
Com.
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
CAS latency = 7
RDQS
DQ
Com.: Command Addr.: Address B / C
B / Cx: Bank / Column address x RD: DTD: N/D : Dx#: READ DTERDIS NOP or Deselect Data from B / Cx
Don't Care DQs : Terminations off RDQS : Not driven
Figure 47
DTERDIS Command followed by DTERDIS
1. At least 1NOP is required between 2 DTERDIS commands. This correspond to a Read to Read transistion on the other memory in a 2 rank system. 2. CAS Latency 7 is used as an example. 3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4 clocks. 4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case, RDQS would be driven by the second Graphics DRAM.
Data Sheet
65
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.8.2
DTERDIS followed by READ
0 CLK# CLK Com. DTD
1
2
5
6
7
8
9
12
13
14
15
16
17
N/D
N/D
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/Cx CAS latency = 7
RDQS
DQ
Dx0
Dx1 Dx2 Dx3
Com.
DTD
N/D
N/D
N/D
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/Cx CAS latency = 7
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Com.: Command Addr.: Address B / C
B / Cx: RD: DTD: N/D: Dx#:
Bank / Column address x READ DTERDIS NOP or Deselect Data from B / Cx
Don't Care DQs : Terminations off RDQS : Not driven
Figure 48
DTERDIS Command followed by READ
1. At least 3 NOPs are required between a DTERDIS command and a READ command in order to avoid contention on the RDQS bus in a 2 rank system. 2. CAS Latency 7 is used as an example. 3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4 clocks.
Data Sheet
66
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.8.3
0 CLK# CLK
DTERDIS followed by Write
1 2 3 6 7 8 9 10 11 12 13
Com.
DTD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
Addr.
B/Cw CAS latency = 7 Write latency = 3
WDQS
DQ
D0w
D1w
D2w
D3w
DTD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cw CAS latency = 8 Write latency = 4
WDQS
DQ
D0w
D1w
D2w
B / Cw: WR: DTD: DES:
Bank / Column address for WRITE WRITE DTERDIS Deselect
Dxw: WRITE Data from B / C Com.: Command Addr.: Address B / C
Don't Care DQs : Terminations off
Figure 49
DTERDIS Command followed by Write
1. Write shown with nominal value of tDQSS. 2. WDQS can only transition when data is applied at the chip input and during pre- and postambles 3. The minimum distance between DTERDIS and Write is (CL - WL + BL/2 +2) clocks.
Data Sheet
67
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
Functional Description
www.DataShe
4.9
CLK# CLK
Precharge (PRE/PREALL)
The Precharge command is used to deactivate the open row in a particular bank (PRE) or the open rows in all banks (PREALL). The bank(s) will enter the idle state and be available again for a new row access after the time tRP. A8/AP sampled with the PRE command determines whether one or all banks are to be precharged. For PRE commands BA0, BA1 and BA2 select the bank. For PREALL inputs BA0, BA1 and BA2 are "Don't Care". The PRE/PREALL command may not be given unless the tRAS requirement is met for the selected bank (PRE), or for all banks (PREALL).
CKE
CS#
RAS#
CAS#
WE#
A0-7,9-11
A8
ALL
ALL: High selects all banks / Low selects Bank BA BA: Bank Address Don't Care
BA0-BA2
BA
Figure 50 Table 21 A8 / AP 0 0 0 0 0 0 0 0 1
Precharge Command BA02, BA1 and BA0 precharge bank selection BA2 0 0 0 0 1 1 1 1 X BA1 0 0 1 1 0 0 1 1 X BA0 0 1 0 1 0 1 0 1 X precharged bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7 only All banks
Data Sheet
68
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
CLK# CLK Command ACT NOP PRE NOP NOP ACT
A0 - A11
Row
Row
BA0 - BA2
B.X t RAS t RC
B.X t RP
B.X
PRE: Precharge ACT: Activate Row: Row Address B.X: Bank X Don't Care
Figure 51
Precharge Timing
Data Sheet
69
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.10
Auto Refresh Command (AREF)
CLK# CLK
CKE
CS#
AREF is used to do a refresh cycle on one row in each bank. The addresses are generated by an internal refresh controller; external address pins are "DON'T CARE". All banks must be idle before the AREF command can be applied. The delay between the AREF command and the next ACT or subsequent AREF must be at least tRFC(min). The refresh period starts when the AREF command is entered and ends tRFC later at which time all banks will be in the idle state. Within a period of tREF the whole memory has to be refreshed. The average periodic interval time from AREF to AREF is then tREFI. To improve efficiency bursts of AREF commands can be used. Such bursts may consist of maximum 8 AREF commands. tRFC(min) is the minimum required time between two AREF commands inside of one AREF burst. According to the number of AREF commands in one burst the average required time from one AREF burst to the next can be increased. Example: If the AREF bursts consists of 8 AREF commands, the average time from one AREF burst to the next is 8* tREFI. The AREF command generates an update of the OCD output impedance and of the addresses, commands and DQ terminations. The timing parameter tKO (see Chapter 4.2.2 must be met.
RAS#
CAS#
WE#
A0-A11
BA: Bank Address
BA0-BA2
Don't Care
Figure 52
Auto Refresh Command
CLK# CLK Command PRE ARF NOP A.C. NOP ARF NOP
CKE
tRP
tRFC tREFI
A.C.: AREF or ACT Command ARF: Auto Refresh Don't Care
Figure 53
Auto Refresh Cycle
Data Sheet
70
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.11 4.11.1
Self-Refresh Self-Refresh Entry (SREFEN)
CLK# CLK
CKE
CS#
The Self-Refresh mode can be used to retain data in the GDDR3 Graphics RAM even if the rest of the system is powered down. When in the Self-Refresh mode, the GDDR3 Graphics RAM retains data without external clocking. The Self-Refresh command is initiated like an Auto-Refresh command except CKE is disabled (LOW). Self Refresh Entry is only possible if all banks are precharged and tRP is met. The GDDR3 Graphics RAM has a build-in timer to accomodate Self-Refresh operation. The Self-Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the command is registered, CKE must be held LOW to keep the device in Self-Refresh mode. When the has entered the Self-Refresh mode, all external control signals, except CKE are disabled. The address, command and data terminators remain on. The DLL and the clock are internally disabled to save power. The user may halt the external clock while the device is in Self-Refresh mode the next clock after Self-Refresh entry, however the clock must be restarted before the device can exit Self-Refresh operation.
RAS#
CAS#
WE#
A0-A7
A9-A11
A8
BA0-BA2
Don't Care
Figure 54
Self-Refresh Entry Command
CLK# CLK
Command
PA
AREF
1 Clock
CKE t RP
CLK/CLK# may be halted
PA.: Precharge ALL Command (or last of PREs to each bank) SRF: Self Refresh Command Don't Care
Figure 55
Self Refresh Entry
Data Sheet
71
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.12
Self-Refresh Exit (SREFEX)
CLK# CLK
CKE
To exit the Self Refresh Mode, a stable external clock is needed before setting CKE high asynchronously. Once the Self-Refresh Exit command is registered, a delay equal or longer than tXSC must be satisfied before any command can be applied. During this time, the DLL is automatically enabled, reset and calibrated. CKE must remain HIGH for the entire Self-Refresh exit period and commands must be gated off with CS held HIGH. Alternately, NOP commands may be registered on each positive clock edge during the Self Refresh exit interval.
CS#
RAS#
CAS#
WE#
A0-A11
A9-A11
Don't Care
Figure 56
Self Refresh Exit Command
CLK# CLK Command N/D N/D N/D A.C.
CKE tXSC
CLK, CLK# must be stable
A.C.: Any Command N / D: NOP or DESEL Command Don't Care
Figure 57
Self Refresh Exit
Data Sheet
72
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.13
Power-Down
CLK# CLK
defined one clock after the rising edge of the Write Postamble. For Read with Autoprecharge and Write with Autoprecharge, the internal Autoprecharge must be completed before entering Power-Down.
1 2
CKE
CS#
RAS#
CAS#
WE#
A0-A11
Power-Down is entered when CKE is registered LOW. (No access can be in progress. "Access" means as well READ or WRITE to a second memory sharing the data bus in a dual rank system.) If Power-Down occurs when all banks are idle, this mode is referred to as Precharge Power-Down; if Power-Down occurs when there is a row active in any bank, this mode is referred to as Active Power-Down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE. For maximum power saving, the user has the option of disabling the DLL prior to entering powerdown. In that case the DLL must be enabled and reset after exiting power-down, and 1000 cycles must occur before a READ command can be issued.
1: DESEL, 2: NOP Don't Care
BA0-BA2
Figure 58
Power Down Command
The requires CKE to be active at all times an access is in progress : From the issuing of a READ or WRITE command until completion of the burst. For READs, a burst completion is defined after the rising edge of the Read Postamble. For Writes, a burst completion is
CLK# CLK Comm. N/D N/D N/D
In Power-Down mode, CKE low and a stable clock signal must be maintained at the inputs of the GDDR3 Graphics RAM, all the other input signals are "Don't Care". Power down duration is limited by the refresh requirements of the device. The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESEL command). A valid executable command may be applied tXPN later.
N/D
A.C.
A.C.
CKE tIS Power-Down Mode Entry Power-Down Mode Exit tXPN
N / D: NOP or DESELECT Command Any Command Don't Care
A.C.:
Figure 59
Power-Down Mode
Data Sheet
73
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.14
DLL Off Mode
For very low frequency operations between 100 MHz and 350 MHz the DLL off mode is supported. Entering this mode requires an Extended Mode Register Set command disabling the DLL by setting A0 to 1. For 350 MHz clock speed and faster DLL on mode operation is recommended. Most of the commands and timings described in Chapter 4.5 to Chapter 4.13 are also applicable for DLL off mode. Differences exist for the frequency range, the initialization and the timing of WR command and RD command.
4.14.1
Frequency range in DLL off mode
Operations in DLL off mode are limited to the frequencies between 100 MHz and 350 MHz. Table 22 Parameter DLL off: General Timing Parameter for -16 and -20 speed sorts Read Latency Symbol Limit Values -16 min Clock DLL off mode System Frequency 9 8 7 max 350 350 350 -20 min 100 100 100 max 350 350 350 MHz MHz MHz Unit Note
fCK9 fCK8 fCK7
100 100 100
4.14.2
Initialization in DLL off mode
VDD VDDQ VREF
t ATS RES
t ATH
CKE CLK# CLK Com. DES DES PA EMR MRS PA ARF ARF A.C.
A6
min. 200 s VDD and CLK stable
min. 700
cycles
t RP
t MRD
t MRD
t RP min. 300
t RFC cycles
t RFC
MRS: MRS command EMR: EMRS command DES : Deselect
PA: A.C.:
PREALL command Any command Don't Care
ARF: AUTO REFRESH command
Figure 60
DLL off: Power Up Sequence
Data Sheet
74
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.14.3
Table 23 Parameter
Writes (WR) in DLL off mode
General Timing Parameter Symbol Limit Values -16 min max -20 min max ns ns ns ns ns ns
(WL*tCK) - 0.5 (WL*tCK) + 0.5 0.88 0.63 1.0 8 14 -- -- 1.5 -- --
Unit
Write comm. to the first DQS latching transition Data-in and DM input pulse width (each input) DQS Write Preamble Time DQS Write Postamble Time Write to Read Write to Precharge
tDQSS tDIPW tWPRE tWPST tWTR tWR
(WL*tCK) - 0.5 (WL*tCK) + 0.5 0.77 0.55 0.88 8 14 -- -- 1.32 -- --
Figure 61
DLL off: Write followed by Read
Data Sheet
75
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
0 CLK# CLK Com .
1
2
3
4
5
6
7
8
9
WR
DES
DES
DES
DES
DES
PRE
DES
DES
DES
Addr.
B/C
B
WR
DES
DES
DES
DES
DES
DES
PRE
DES
DES
B/C
B
WL = 3 WDQS
t WR
t RP
DQ
D0
D1
D2
D3
WR
DES
DES
DES
DES
DES
DES
DES
PRE
DES
B/C
B
WL = 4 WDQS
t WR
t RP
DQ
D0
D1
D2
D3
B / C: Bank / Column address WR: PRE: Dx#: Dy#: WRITE PRECHARGE Data to B / Cx Data to B / Cy
Com.: Command Addr.: Address B / C WL: DES: Write Latency Deselect
Don't Care
Figure 62
Write followed by Precharge
4.14.4
Reads (RD) in DLL off mode
Definition of read latency in DLL off mode is different from DLL on mode. Since in DLL off mode the read data is not synchronized to the CLK, the internal access time to the memory array becomes visible. Read data in DLL off mode appears on the I/O balls after (CL - 1) + tAC. CL is the value for the read latency which is set in the Mode Register.
Data Sheet
76
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
Table 24 Parameter
Read Timing Parameter Read Latency Symbol Limit Values -16 min max -20 min max Unit Note
Read to Write command delay Data Access Time from Clock in DLL off mode DQS edge to Clock edge skew in DLL off mode
tRTW tACOFF tDQSCK
3 6
tRTW(min) = (CL+4-WL)
2.4 2.4 6.2 6.2 2.4 2.4 6.2 6.2
tCK
ns ns
Read Cycle Timing Parameters for Data and Data Strobe
0 CLK# CLK
1
2
7
8
9
10
Com.
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/C
CAS latency = 7
t DQSCK
RDQS
DQ t ACOFF CAS latency = 8
D0
D1
D2
D3
t DQSCK
RDQS
DQ tACOFF
D0
D1
D2
D3
B / C: Bank / Column address RD: Dx: Don't Care READ Data from B / C
Com.: Command Addr.: Address B / C N/D: NOP or Deselect
Figure 63
DLL off: Read Burst
Data Sheet
77
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
0 CLK# CLK
1
2
3
6
7
8
9
10
11
12
13
Com.
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
Addr.
B/Cr
B/Cw
CAS latency = 7 t RTW t DQSCKOFF RDQS Write latency = 3 WDQS
DQ
t ACOFF
D0r
D1r
D2r
D3r
D0w
D1w
D2w
D0w
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cr
B/Cw
CAS latency = 8 t RTW tDQSCKOFF
RDQS Write latency = 4 WDQS
DQ t ACOFF
D0r
D1r
D2r
D3r
D0w
D1w
D2w
B / Cr: Bank / Column address for READ B / Cw: Bank / Column address for WRITE RD: WR: DES: READ WRITE Deselect
Dxr: Dxw:
READ Data from B / C WRITE Data from B / C
Don't Care DQs : Terminations off RDQS : Not driven
Com.: Command Addr.: Address B / C
Figure 64
DLL off: Read followed by Write
Data Sheet
78
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Functional Description
4.14.5
Self Refresh in DLL off mode
Self Refresh in DLL off mode is basically the same like in DLL on mode. Table 25 Parameter Self Refresh Exit Timing Parameter Read Latency Symbol Limit Values -16 min Self Refresh Exit Time max -- -20 min 700 max -- tCK Unit Note
tXSC
700
Data Sheet
79
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
Electrical Characteristics
www.DataShe
5
5.1
Electrical Characteristics
Absolute Maximum Ratings and Operation Conditions
Table 26 Parameter
Absolute Maximum Ratings Symbol Rating min. max. 2.5 2.5 V V V V C C mA -0.5 -0.5 -0.5 -0.5 -55 -- Unit
Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Storage Temperature Junction Temperature Short Circuit Output Current
VDD VDDQ VIN VOUT TSTG TJ IOUT
2.5 2.5
+150 +125 50
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Data Sheet
80
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.2 5.2.1
Table 27 Parameter
DC Operation Conditions Recommended Power & DC Operation Conditions.
Power & DC Operation Conditions.( 0 C Tc 85 C) Symbol Limit Values min. typ. 2.0 2.0 1.8 1.8 -- -- -- -- max. 2.1 2.1 1.9 1.9 0.71*VDDQ 0.8 +5.0 +5.0 1.9 1.9 1.7 1.7 0.69*VDDQ -- -5.0 -5.0 Unit Note s V V V V V V A A A
5) 5) 1)2) 1)2) 1)3) 1)3) 4)
Power Supply Voltage Power Supply Voltage for I/O Buffer Power Supply Voltage Power Supply Voltage for I/O Buffer Reference Voltage Output Low Voltage Input leakage current CLK Input leakage current
Output leakage current -5.0 -- +5.0 1) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
VDD, VDDA VDDQ VDD, VDDA VDDQ VREF VOL(DC) IIL IILC IOL
2) HYB18H512321AF-12/14/16/20 3) HYB18H512321AFL14/16/20 4) VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed 2% VREF (DC). Thus, from 70% of VDDQ, VREF is allowed 19mV for DC error and an additionnal 27mV for AC noise. 5) IIL and IOL are measured with ODT disabled.
Data Sheet
81
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.3 5.4
Table 28 Parameter
DC & AC Logic Input Levels Differential Clock DC and AC Levels
DC & AC Logic Input Levels ( 0 C Tc 85 C) Symbol Limit Values min. max. -- Unit Note s V V V V V V V
4) 1) 1) 2) 3)
Input logic high voltage, DC Input logic low voltage, DC Input logic high voltage, AC Input logic low voltage, AC Input logic high, DC, RESET pin Input logic low, DC, RESET pin Input Logic High, DC, MF pin
Input Logic Low,DC, MF pin -0.3 0 V 1) The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. 2) Input slew rate = 3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew rates are measured between VIL(DC) and VIH(DC). 3) VIH overshoot : VIH(max) = VDDQ+0.5V for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. VIL undershoot: VIL(min) = 0V for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate.
4) The MF pin must be hard-wired on board to either VDD or VSS.
VIH(DC) VIL(DC) VIH(AC) VIL(AC) VIHR(DC) VILR(DC) VIHMF(DC) VILMF(DC)
VREF + 0.15
--
VREF -0.15
--
VREF + 0.25
-- 0.65.VDDQ -0.3
, ,
VREF - 0.25 VDDQ + 0.3
0.35.VDDQ
2) 3)
VDD
VDD + 0.3
Table 29 Parameter
Differential Clock DC and AC Input conditions ( 0 C Tc 85 C) Symbol Limit Values min. max. 0.7 x VDDQ + 0.10 V
1) 1) 1)
Unit
Notes
Clock Input Mid-Point Voltage, CLK and CLK VMP(DC)
0.7 x VDDQ - 0.10 0.42 0.3 0.5
VIN(DC) Clock DC Input Differential Voltage, CLK and VID(DC)
Clock Input Voltage Level, CLK and CLK CLK Clock AC Input Differential Voltage, CLK and VID(AC) CLK
VDDQ + 0.3 VDDQ VDDQ + 0.5
V V V
1)2)
1)3) AC Differential Crossing Point Input Voltage VIX(AC) 0.7 x VDDQ - 0.15 0.7 x VDDQ + 0.15 V 1) All voltages referenced to VSS. 2) VID is the magnitude of the difference between the input level on CLK and the input level on CLK. 3) The value of VIX is expected to equal 0.7 x VDDQ of the transmitting device and must track variations in the DC level of the same.
Data Sheet
82
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.5
Output Test Conditions
VDDQ
60 Ohm
DQ DQS
Test point
Figure 65
Output Test Circuit
5.6
Table 30 Parameter
Pin Capacitances
Pin Capacitances (VDDQ = 1.8V, TA = 25C, f= 1MHz) Symbol CI,CCK Min 1.5 Max 2.5 Unit pF Notes
Input capacitance: A0-A11, BA0-2,CKE, CS, CAS, RAS, WE, CKE, RES,CLK,CLK Input capacitance: DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0DM3
CIO
2.5
3.5
pF
Data Sheet
83
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.7 5.7.1
Driver current characteristics Driver IV characteristics at 40 Ohms
Figure 66 represents the driver Pull-Down and Pull-Up IV characteristics under process, voltage and temperature best and worst case conditions. The actual Driver Pull-Down and Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 , setting the nominal driver output impedance to 40 .
Pull-Down Characterstics 50 45 40 35 Iout (mA) 30 20 15 10 5 0 0,0 0,5 1,0 Vout (V) 1,5 2,0 25
Pull-Up Characterstics 0,0 0 -5 -10 -15 Iout (mA) -20 -25 -30 -35 -40 -45 -50 VDDQ - Vout (V) 0,5 1,0 1,5 2,0
Figure 66
40 Ohm Driver Pull-Down and Pull-Up characteristics
Table 31 lists the numerical values of the minimum and maximum allowed values of the output driver Pull-Down and Pull-Up IV characteristics. Table 31 Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Data Sheet Programmed Driver IV Characterisitcs at 40 Ohm Pull-Down Current (mA) Minimum 2.32 4.56 6.69 8.74 10.70 12.56 14.34 16.01 17.61 19.11 20.53 21.92 23.29 24.65 26.00 27.35 28.70 30.08 -- -- Maximum 3.04 5.98 8.82 11.56 14.19 16.72 19.14 21.44 23.61 26.10 28.45 30.45 32.73 34.95 37.10 39.15 41.01 42.53 43.71 44.89 84 Pull-Up Current (mA) Minimum -2.44 -4.79 -7.03 -9.18 -11.23 -13.17 -15.01 -16.74 -18.37 -19.90 .21.34 -22.72 -24.07 -25.40 -26.73 -28.06 -29.37 -30.66 -- -- Maximum -3.27 -6.42 -9.45 -12.37 -15.17 -17.83 -20.37 -22.78 -25.04 -27.17 -29.17 -31.25 -33.00 -35.00 -37.00 -39.14 -41.25 -43.29 -45.23 -47.07 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.7.2
Termination IV Characteristic at 60 Ohms
Figure 67 represents the DQ termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual DQ termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 , setting the nominal DQ termination impedance to 60 . (Extended Mode Register programmed to ZQ/4).
60 Ohm Termination Characterstics 0,0 0 -5 -10 Iout (mA) -15 -20 -25 -30 -35 VDDQ - Vout (V) 0,5 1,0 1,5 2,0
Figure 67
60 Ohm Active Termination Characteristic
Table 32 lists the numerical values of the minimum and maximum allowed values of the output driver termination IV characteristic. Table 32 Voltage (V) Programmed Terminator Characteristics at 60 Ohm Terminator Pull-Up Current (mA) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -1.63 -3.19 -4.69 -6.12 -7.49 -8.78 -10.01 -11.16 -12.25 -13.27 Maximum -2.18 -4.28 -6.30 -8.25 -10.11 -11.89 -13.58 -15.19 -16.69 -18.11 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Voltage (V) Terminator Pull-Up Current (mA) Minimum -14.23 -15.14 -16.04 -16.94 -17.82 -18.70 -19.58 -20.44 -- -- Maximum -19.45 -20.83 -22.00 -23.33 -24.67 -26.09 -27.50 -28.86 -30.15 -31.38
Data Sheet
85
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.8
Termination IV Characteristic at 120 Ohms
Figure 68 represents the DQ or ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 , setting the nominal termination impedance to 120 . (Extended Mode Register programmed to ZQ/2 for DQ terminations or CKE = 0 at the RES transition during Power-Up for ADD/CMD terminations).
120 Ohm Termination Characterstics 0,0 0 -2 -4 Iout (mA) -6 -8 -10 -12 -14 -16 VDDQ - Vout (V) 0,5 1,0 1,5 2,0
Figure 68
120 Ohm Active Termination Characteristics
Table 33 lists the numerical values of the minimum and maximum allowed values of the termination IV characteristic. Table 33 Voltage (V) Programmed Terminator Characteristics af 120 Ohm Terminator Pull-Up Current (mA) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -0.81 -1.60 -2.34 -3.06 -3.74 -4.39 -5.00 -5.58 -6.12 -6.63 Maximum -1.09 -2.14 -3.15 -4.12 -5.06 -5.94 -6.79 -7.59 -8.35 -9.06 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Voltage (V) Terminator Pull-Up Current (mA) Minimum -7.11 -7.57 -8.02 -8.47 -8.91 -9.35 -9.79 -10.22 -- -- Maximum -9.72 -10.42 -11.00 -11.67 -12.33 -13.05 -13.75 -14.43 -15.08 -15.69
Data Sheet
86
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.9
Termination IV Characteristic at 240 Ohms
Figure 69 represents the ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual ADD/CMD termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 , setting the nominal termination impedance to 240 . (CKE = 1at the RES transition during Power-Up for ADD/CMD terminations).
240 Ohm Termination Characterstics 0,0 0,0 -1,0 -2,0 Iout (mA) -3,0 -4,0 -5,0 -6,0 -7,0 -8,0 VDDQ - Vout (V) 0,5 1,0 1,5 2,0
Figure 69
240 Ohm Active Termination Characteristic
Table 34 lists the numerical values of the minimum and maximum allowed values of the ADD/CMD termination IV characteristic. Table 34 Voltage (V) Programmed Terminator Characteristic at 240 Ohm Terminator Pull-Up Current (mA) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -0.41 -0.80 -1.17 -1.53 -1.87 -2.20 -2.50 -2.79 -3.06 -3.32 Maximum -0.55 -1.07 -1.58 -2.06 -2.53 -2.97 -3.40 -3.80 -4.17 -4.53 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Voltage (V) Terminator Pull-Up Current (mA) Minimum -3.56 -3.79 -4.01 -4.23 -4.46 -4.68 -4.90 -5.11 -- -- Maximum -4.86 -5.21 -5.50 -5.83 -6.17 -6.52 -6.88 -7.21 -7.54 -7.85
Data Sheet
87
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.10 5.10.1
Table 35 Parameter
Operating Currents Operating Current Ratings ( HYB18H512321AF-12/14/16/20 )
Operating Current Ratings ( 0 C Tc 85 C) Symbol -12 typ. -14 typ. 453 425 243 316 287 244 411 725 581 548 366 8 Values -16 typ. 406 383 215 280 254 216 364 642 511 500 324 8 -20 typ. 362 348 186 243 221 187 317 558 445 409 281 8 641 mA mA mA mA mA mA mA mA mA mA mA mA mA
1) 2) 3)
Unit Notes
Operating Current Operating Current Precharge Power-Down Standby Current Precharge Floating Standby Current Precharge Quiet Standby Current Active Power-Down Standy Current Active Standby Current
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P
498 463 271 352 319 272 456 805 641 587 408 8
,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,,
1) 2) 3) 1) 2) 3)
1) 2) 3)
1) 2) 3)
1) 2) 3)
IDD3N Operating Current Burst Read IDD4R Operating Current Burst Write IDD4W Auto-Refresh Current IDD5B
(tRC=min(tRFC)) Auto-Refresh Current at tREFI Self Refresh Current
1) 2) 3) 1) 2) 3) 1) 2) 3) 1) 2) 3)
733 703 671 Operating Current 1) IDD specifications are tested after the device is properly initialized. 2) Input slew rate = 3V/ns. 3) Measured with Output open and On Die termination off. 4) Enables on-chip refresh and address counter.
IDD5D IDD6 IDD7
1) 2) 3) 1) 2) 3) 4)
,,,
1) 2) 3)
Data Sheet
88
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.10.2
Table 36 Parameter
Operating Current Ratings (HYB18H512321AFL14/16/20)
Operating Current Ratings ( 0 C Tc 85 C) Symbol -14 typ. Values -16 typ. 367 346 192 250 228 195 328 610 466 472 290 8 -20 typ. 328 315 167 218 199 169 286 501 403 386 252 8 600 mA mA mA mA mA mA mA mA mA mA mA mA mA
1) 2) 3)
Unit Notes
Operating Current Operating Current Precharge Power-Down Standby Current Precharge Floating Standby Current Precharge Quiet Standby Current Active Power-Down Standy Current Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRC=min(tRFC)) Auto-Refresh Current at tREFI Self Refresh Current
Operating Current 654 627 1) IDD specifications are tested after the device is properly initialized. 2) Input slew rate = 3V/ns. 3) Measured with Output open and On Die termination off. 4) Enables on-chip refresh and address counter.
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
406 384 218 283 257 220 369 648 521 514 328 8
,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,,
1) 2) 3) 1) 2) 3) 1) 2) 3) 1) 2) 3) 1) 2) 3) 1) 2) 3) 1) 2) 3) 1) 2) 3) 1) 2) 3) 1) 2) 3) 1) 2) 3) 4)
,,,
1) 2) 3)
Data Sheet
89
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.11
Table 37
Operating Current Measurement Conditions
Operating Current Measurement Conditions Operating Current - One bank, Activate - Precharge tCK=min(tCK), tRC=min(tRC) Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH between valid commands. Operating Current - One bank, Activate - Read - Precharge One bank is accessed with tCK=min(tCK), tRC=min(tRC), CL = CL(min), Address and control inputs are SWITCHING; CS = HIGH between valid commands. Iout=0mA Precharge Power-Down Standby Current All banks idle, power-down mode, CKE is LOW, tCK=min(tCK), Data bus inputs are STABLE (HIGH). Precharge Floating Standby Current All banks idle; CS is HIGH, CKE is HIGH, tCK=min(tCK); Address and control inputs are SWITCHING; Data bus input are STABLE (HIGH). Precharge Quiet Standby Current CS is HIGH, all banks idle, CKE is HIGH, tCK=min(tCK), Address and other control inputs STABLE (HIGH), Data bus inputs are STABLE (HIGH). Active Power-Down Standby Current One bank active, CKE is LOW, Address and control inputs are STABLE (HIGH); Data bus inputs are STABLE (HIGH); standard active power-down mode. Active Standby Current One bank active, CS is HIGH, CKE is HIGH, tRAS= tRAS,max, tCK=min(tCK); Address and control inputs are SWITCHING; Data bus inputs are SWITCHING. Operating Current - Burst Read One bank active; Continuous read bursts, CL = CL(min); tCK=min(tCK); tRAS= tRAS,max; Address and control inputs are SWITCHING; Iout = 0 mA. Operating Current - Burst Write One bank active; Continuous write bursts; tCK=min(tCK); Address and control inputs are SWITCHING; Data bus inputs are SWITCHING. Burst Auto Refresh Current Refresh command at tRFC=min(tRFC); tCK=min(tCK); CKE is HIGH, CS is HIGH between all valid commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING. Distributed Auto Refresh Current tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING. Self Refresh Current CKE max(VIL), external clock off, CK and CK LOW; Address and control inputs are STABLE (HIGH); Data Bus inputs are STABLE (HIGH). Operating Bank Interleave Read Current 1. All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0 mA; Address and control inputs are STABLE (HIGH) during DESELECT; Data bus inputs are SWITCHING. 2: Timing pattern: tbd.
Symbol Parameter/Condition
IDD0
IDD1
IDD2P IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
1. 0 C Tc 85 C 2. Data Bus consists of DQ, DM, WDQS. Data Sheet 90 Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics 3. Definitions for IDD : LOW is defined as VIN = 0.4 x VDDQ; HIGH is defined as VIN = VDDQ; TABLE is defined as inputs are stable at a HIGH level. SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals, and inputs changing 50% of each data transfer for DQ signals. 4. Legend: A=Active; RA=Read with Autoprecharge; D=DESELECT.
Data Sheet
91
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.12
Table 38 Parameter
AC Timings ( HYB18H512321AF-12/14/16/20)
Timing Parameters (HYB18H512321AF-12/14/16/20) CAS latency Symbol -12 min max
800 700 650 550 500 0.55 0.55 -- -- -- --
Limit Values -14 min
3501) 350 350 350 350
1) 1) 1) 1)
Unit -20 max min max MHz
-16 max
700 650 600 500 450 0.55 0.55 -- -- -- -- 350 350 350 350
1) 1) 1) 1)
min
Clock and Clock Enable System frequency CL= 11 CL =10 CL = 9 CL = 8 CL = 7 Clock high level width Clock low level width Minimum clock half period Address/Command input setup time
fCK11 fCK10 fCK9 fCK8 fCK7 tCH tCL tHP tIS
3501) 350 350 350 350
1) 1) 1) 1)
600 550 500 450 0.55 0.55 -- -- -- -- 350 350
1) 1)
MHz MHz
500 450 0.55 0.55 -- -- -- --
MHz MHz
0.45 0.45 0.45 0.3 0.3 0.7
0.45 0.45 0.45 0.35 0.35 0.7
0.45 0.45 0.45 0.4 0.4 0.7
0.45 0.45 0.45 0.5 0.5 0.7
tCK tCK tCK
ns ns
2)
Command and Address Setup and Hold Timing
Address/Command input hold tIH time Address/Command input pulse width Mode Register Set Timing Mode Register Set cycle time Mode Register Set to READ timing Row Timing Row Cycle Time Row Active Time ACT(a) to ACT(b) Command period Row Precharge Time Reads Row to Column Delay Time for tRCDWR Writes Column Timing CAS(a) to CAS(b) Command period Write to Read Command Delay
tIPW
tCK
tMRD tMRDR
6 12
-- --
6 12
-- --
6 12
-- --
6 12
-- --
tCK tCK
3)4) 3)
tRC tRAS tRRD
32 21 8 13 12
-- -- -- -- --
30 18 7 12 11
-- -- -- -- --
27 17 6 11 10
-- -- -- -- --
23 14 5 9 8
-- -- -- -- --
tck tck tck tck tck tck
5)
tRP Row to Column Delay Time for tRCDRD
tRCDWR(min) = tRCDRD(min) - (WL + 1) x tCK
tCCD tWTR
2 6
-- --
2 5
-- --
2 5
-- --
2 4
-- --
tCK
tck
6)
7)
Read to Write command delay tRTW Write command to first WDQS tDQSS latching transition Data Sheet
WL- 0.25 WL+ 0.25
tRTW(min)= (CL + BL/2 +2 -WL) WL- 0.25 WL+ 0.25 WL- 0.25 WL+ 0.25 WL 0.25 WL+ 0.25
tCK tCK
8)
Write Cycle Timing Parameters for Data and Data Strobe
92
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics Table 38 Parameter Timing Parameters (HYB18H512321AF-12/14/16/20) CAS latency Symbol -12 min Data-in and Data Mask to WDQS Setup Time Data-in and Data Mask to WDQS Hold Time Data-in and DM input pulse width (each input) DQS input low pulse width DQS input high pulse width DQS Write Preamble Time DQS Write Postamble Time Write Recovery Time max
-- -- -- -- -- 1.25 1.25 -- 0.22 1.25 1.25 tACmax tACmax 0.22 0.140 0.140
Limit Values -14 min
0.18 0.18 0.40 0.40 0.40 0.75 0.75 8 -0.25 0.75 0.75 tACmin tACmin -0.25 -- -- tHP-tQHS
Unit -20 max
-- -- -- -- -- 1.25 1.25 -- 0.28 1.25 1.25 tACmax tACmax 0.28 0.180 0.180
-16 max
-- -- -- -- -- 1.25 1.25 -- 0.25 1.25 1.25 tACmax tACmax 0.25 0.160 0.160
min
0.20 0.20 0.40 0.40 0.40 0.75 0.75 7 -0.28 0.75 0.75 tACmin tACmin -0.28 -- -- tHP-tQHS
min
0.24 0.24 0.40 0.40 0.40 0.75 0.75 6 -0.35 0.75 0.75 tACmin tACmin -0.35 -- -- tHP-tQHS
max
-- -- -- -- -- 1.25 1.25 -- 0.35 1.25 1.25 tACmax tACmax 0.35 0.225 0.225
tDS tDH tDIPW tDQSL tDQSH tWPRE tWPST tWR
0.16 0.16 0.40 0.40 0.40 0.75 0.75 9 -0.22 0.75 0.75 tACmin tACmin -0.22 -- -- tHP-tQHS
ns ns
tCK tCK tCK tCK tCK tCK
ns
7)
Read Cycle Timing Parameters for Data and Data Strobe Data Access Time from Clock tAC
tRPRE Read Postamble tRPST Data-out high impedance time tHZ
from CLK Data-out low impedance time from CLK
Read Preamble
tCK tCK
ns ns ns ns ns ns
9)
tLZ
DQS edge to Clock edge skew tDQSCK DQS edge to output data edge tDQSQ skew Data hold skew factor Data output hold time from DQS Refresh/Power Down Timing Refresh Period (8192 cycles) interval Delay from AREF to next ACT/ tRFC AREF Self Refresh Exit time Power Down Exit time Other Timing Parameters RES to CKE setup timing
tQHS tQH
tREF Average periodic Auto Refresh tREFI
--
32 3.9
--
32 3.9
--
32 3.9
--
32 3.9
ms s ns
52.0 1000 7 10 10 10
-- -- -- -- -- --
52.0 1000 6 10 10 10
-- -- -- -- -- --
52.8 1000 5 10 10 10
-- -- -- -- -- --
54 1000 4 10 10 10
-- -- -- -- -- --
tXSC tXPN
tCK tCK
ns ns ns
tATS RES to CKE hold timing tATH Termination update Keep Out tKO
timing
Data Sheet
93
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics Table 38 Parameter Timing Parameters (HYB18H512321AF-12/14/16/20) CAS latency Symbol -12 min Rev. ID EMRS to DQ on timing tRIDon REV. ID EMRS to DQ off timing
-- --
Limit Values -14 max
20 20
Unit -20 max
20 20
-16 max
20 20
min
-- --
min
-- --
min
-- --
max
20 20
ns ns
tRIDoff
1) DLLon mode 2) tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs 3) This value of tMRD applies only to the case where the 'DLL reset ' bit is not activated. 4) tMRD is defined from MRS to any other command then READ. 5) tRAS,max is 8*tREFi 6) tCCD is either for gapless consecutive reads or gapless consecutive writes. BL =4
7) WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal. 8) Please round up tRTW to the next integer of tCK.
9) This parameter is defined per byte.
Data Sheet
94
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
5.13
Table 39 Parameter
AC Timings ( HYB18H512321AFL14/16/20)
Timing Parameters (HYB18H512321AFL14/16/20) CAS latency Symbol Limit values -14 min max
700 650 600 500 450 0.55 0.55 -- -- -- --
Unit -16 min
3501) 350 350 350 350
1) 1) 1) 1)
Notes
-20 max
600 550 500 450 400 0.55 0.55 -- -- -- -- 350 350 350 350
1) 1) 1) 1)
min
max
MHz 500 450 400 350 0.55 0.55 -- -- -- -- MHz MHz MHz MHz tCK tCK tCK ns ns tCK
2)
Clock and Clock Enable System frequency CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 Clock high level width Clock low level width Minimum clock half period Address/Command input setup time Address/Command input pulse width Mode Register Set Timing Mode Register Set cycle time Row Timing
fCK11 fCK10 fCK9 fCK8 fCK7 tCH tCL tHP tIS
3501) 350 350 350 350
1) 1) 1) 1)
0.45 0.45 0.45 0.35 0.35 0.7
0.45 0.45 0.45 0.4 0.4 0.7
0.45 0.45 0.45 0.5 0.5 0.7
Command and Address Setup and Hold Timing
Address/Command input hold time tIH
tIPW
tMRD
6 12 30 18 7 12 11
-- -- -- -- -- -- --
6 12 27 17 6 11 10
-- -- -- -- -- -- --
6 12 23 14 5 9 8
-- -- -- -- -- -- --
tCK tCK tCK tCK tCK tCK tCK tCK
5) 3)
Mode Register Set to READ timing tMRDR
tRC Row Active Time tRAS ACT(a) to ACT(b) Command period tRRD Row Precharge Time tRP Row to Column Delay Time for tRCDRD
Row Cycle Time Reads Row to Column Delay Time for Writes Column Timing CAS(a) to CAS(b) Command period Write to Read Command Delay Read to Write command delay Write command to first WDQS latching transition Data-in and Data Mask to WDQS Setup Time
tRCDWR
tRCDWR(min) = tRCDRD(min) - (WL + 1) x tCK
tCCD tWTR tRTW tDQSS tDS
2 5
-- --
2 5
-- --
2 4
-- --
tCK tCK tCK
4)
5) 6)
tRTW(min)= (CL + BL/2 +2 -WL) WL- 0.25 0.18 WL+0. WL- 25 0.25 -- 0.20 WL+0 WL .25 0.25 -- 0.24 WL +0.25 --
Write Cycle Timing Parameters for Data and Data Strobe
tCK ns
Data Sheet
95
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics Table 39 Parameter Timing Parameters (HYB18H512321AFL14/16/20) CAS latency Symbol Limit values -14 min Data-in and Data Mask to WDQS Hold Time Data-in and DM input pulse width (each input) DQS input low pulse width DQS input high pulse width DQS Write Preamble Time DQS Write Postamble Time Write Recovery Time Data Access Time from Clock max
-- -- -- -- 1.25 1.25 -- 0.25 1.25 1.25 tACmax tACmax 0.25 0.160 0.160
Unit -16 min
0.20 0.40 0.40 0.40 0.75 0.75 7 -0.28 0.75 0.75 tACmin tACmin -0.28 -- -- tHP-tQHS
Notes
-20 max
-- -- -- -- 1.25 1.25 -- 0.28 1.25 1.25 tACmax tACmax 0.28 0.18 0.18
min
0.24 0.40 0.40 0.40 0.75 0.75 6 -0.35 0.75 0.75 tACmin tACmin -0.35 -- -- tHP-tQHS
max
-- -- -- -- 1.25 1.25 -- 0.35 1.25 1.25 tACmax tACmax 0.35 0.225 0.225 ns tCK tCK tCK tCK tCK tCK ns tCK tCK ns ns ns ns ns ns 32 3.9 ms s ns tCK tCK ns ns ns ns ns
7) 7)
tDH tDIPW tDQSL tDQSH tWPRE tWPST tWR
0.18 0.40 0.40 0.40 0.75 0.75 8 -0.25 0.75 0.75 tACmin tACmin -0.25 -- -- tHP-tQHS --
Read Cycle Timing Parameters for Data and Data Strobe
tAC Read Preamble tRPRE Read Postamble tRPST Data-out high impedance time from tHZ
CLK Data-out low impedance time from tLZ CLK DQS edge to Clock edge skew DQS edge to output data edge skew Data hold skew factor Data output hold time from DQS Refresh/Power Down Timing Refresh Period (8192 cycles) Average periodic Auto Refresh interval Delay from AREF to next ACT/ AREF Self Refresh Exit time Power Down Exit time Other Timing Parameters RES to CKE setup timing RES to CKE hold timing Termination update Keep Out timing Rev. ID EMRS to DQ on timing REV. ID EMRS to DQ off timing
1) DLLon mode 2) tHP is the lesser of 3) tRAS,max is 8*tREFi
tDQSCK tDQSQ tQHS tQH tREF tREFI tRFC tXSC tXPN tATS tATH tKO tRIDon tRIDoff
32 3.9
--
32 3.9
--
52.0 1000 6 10 10 10 -- --
-- -- -- -- -- -- 20 20
52.8 1000 5 10 10 10 -- --
-- -- -- -- -- -- 20 20
54 1000 4 10 10 10 -- --
-- -- -- -- -- -- 20 20
tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs
Data Sheet
96
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Electrical Characteristics
tCCD is either for gapless consecutive reads or gapless consecutive writes. BL =4 5) WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal. 6) Please round up tRTW to the next integer of tCK.
4) 7) This parameter is defined per byte.
Data Sheet
97
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
www..com
Package
6
6.1
Package
Package Outline
Figure 70
PG-TFBGA 136 package (11mm x 14mm)
Note: . The package is conforming with JEDEC MO-207i, VAR DR-z.
Data Sheet
98
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
HYB18H512321AF 512-Mbit GDDR3
Package
www.DataSheet4
6.2
Table 40
Package Thermal Characteristics
PG-TFBGA 136 Package Thermal Resistances Theta_jA Theta_jB 2s0p 1 m/s 32 3 m/s 27 0 m/s 22 1 m/s 19 3 m/s 17 5 2 Theta_jC 1s0p 0 m/s 40
JEDEC Board Air Flow K/W
1. Theta_jA : Junction to Ambient thermal resistance. The values have been obtained by simulation using the conditions stated in the JEDEC JESD-51 standard. 2. Theta_jB : Junction to Board thermal resistance. The value has been obtained by simulation. 3. Theta_jC : Junction to Case thermal resistance. The value has been obtained by simulation.
Data Sheet
99
Rev. 1.73, 2005-08 05122004-B1L1-JEN8
www..com
www.infineon.com
Published by Infineon Technologies AG

▲Up To Search▲

Price & Availability of HYB18H512321AF-12

	To Download HYB18H512321AF-12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .